Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2001-09-27

2002-11-19

Coneo, Kaman D. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S294000, C438S295000, C438S297000, C438S298000, C438S425000, C438S426000, C438S427000, C438S431000, C438S439000, C438S452000

Reexamination Certificate

active

06482718

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a trench isolation structure.
2. Description of the Background Art
FIGS. 12
to
19
are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional trench isolation structure which for example has been announced on June 15 at a symposium on VLSI technology held from June 13 through to June 15 in 2000.
First, after sequential deposition of a thermal oxide film
4
, a polycrystalline silicon layer
3
, and a silicon nitride film
2
on a silicon substrate
1
, as shown in
FIG. 12
, the silicon nitride film
2
, the polycrystalline silicon layer
3
, and the thermal oxide film
4
are patterned to form an opening
20
. More specifically, the patterning of the silicon nitride film
2
, the polycrystalline silicon layer
3
, and the thermal oxide film
4
is performed in such a manner that selective removal using photolithography and dry etching produces the opening
20
, whereby the silicon substrate
1
under the opening
20
is defined as an element isolation region for providing element isolation between semiconductor elements such as MOSFETs and the other part of the silicon substrate
1
as an element forming region.
Using the patterned silicon nitride film
2
as a mask, as shown in
FIG. 13
, the silicon substrate
1
under the opening
20
is selectively etched to form a trench
5
in the upper portion of the silicon substrate
1
.
Then, as shown in
FIG. 14
, thermal oxidation is performed to form a thermal oxide film
6
on the inner wall of the trench
5
. The thermal oxide film
6
is formed in such a manner that silicon on the inner-wall surface of the trench
5
is oxidized to an oxide film.
At this time, part of the polycrystalline silicon layer
3
exposed to the opening
20
is also oxidized, forming polycrystalline silicon oxide areas
6
a.
Thereby, “bird's beak” formed of the oxide films
4
,
6
, and
6
a
is formed in neighborhoods of trench corners (hereinafter referred to as “trench-corner neighboring areas”)
7
.
Then, as shown in
FIG. 15
, a buried oxide film
8
is formed to fill the trench
5
and to cover the whole surface, by TEOS (tetra etyle ortho silicate), HDP-CVD (high density plasma-chemical vapor deposition) or the like.
As shown in
FIG. 16
, planarization is performed with the silicon nitride film
2
as a stopper by using a planarization technique such as etching or chemical-mechanical polishing.
The exposed silicon nitride film
2
and the polycrystalline silicon layer
3
are then selectively and sequentially removed as shown in FIG.
17
.
Also, the thermal oxide film
4
and the polycrystalline silicon oxide areas
6
a
are removed by wet etching as shown in FIG.
18
.
Then, as shown in
FIG. 19
, a gate oxide film
10
of a MOS transistor is formed. Thereafter, conventional manufacturing methods for MOS transistors are applied to form MOS transistors in the element forming region of the silicon substrate
1
which is trench-isolated by the element isolation region or buried oxide film
8
.
In such a manufacturing method, if the relatively thick thermal oxide film
6
of 50 nm thickness is formed on the inner wall of the trench
5
, as shown in
FIG. 18
, an excellent form of isolation with less recessing of the oxide films
6
and
8
can be established in trench-corner neighboring areas
9
(isolation edges). This results from the fact that as shown in
FIG. 14
, the local oxidation of the polycrystalline silicon layer
3
during the formation of the thermal oxide film
6
produces the polycrystalline silicon oxide areas
6
a
and accordingly grows relatively wide “bird's beak” in the horizontal direction of the drawing in the trench-corner neighboring areas
7
. This gives protection to the trench-corner neighboring areas
9
during removal of the thermal oxide film
4
.
Now, in consideration of future device miniaturization, an aspect ratio of the trench in the filling process increases with decreasing isolation spacing (or width of the trench
5
). For example when the isolation spacing is relatively wide, namely 0.35 &mgr;m, and the inner wall of the trench
5
is oxidized with an oxide film of about 50 nm thickness, the film thickness from the interface of the trench
5
will be about half of the above thickness, namely 25 nm. This leaves a sufficient margin of the isolation spacing to be filled (the width of the trench
5
after formation of the thermal oxide film
6
), namely 0.3 &mgr;m (=0.35−(2×0.025)). For example, where the depth of the trench
5
is 0.3 &mgr;m and the height of the mask (the height of a multiple layer stack of the silicon nitride film
2
, the polycrystalline silicon layer
3
, and the thermal oxide film
4
) is 0.1 &mgr;m, the aspect ratio is approximately 1.3(=0.4/0.3).
However, if the isolation spacing is reduced to 0.15 &mgr;m by device miniaturization and the inner wall of the trench
5
is oxidized with an oxide film of about 50 nm thickness, the isolation spacing to be filled becomes considerably narrow, namely 0.1 &mgr;m (=0.15−(2×0.025)). Thus, the aspect ratio considerably increases, namely 4.0(=0.4/0.1), under the same conditions as above (i.e., where the depth of the trench
5
is 0.3 &mgr;m and the mask height is 0.1 &mgr;m).
Such an increase in the aspect ratio has been known to cause a failure in filling the trench
5
with the buried oxide film
8
, and as shown in
FIG. 20
, increases the risk of forming an improperly filled area
14
during the filling of the trench
5
with the buried oxide film
8
. In order to inhibit an increase in the aspect ratio, therefore, the thermal oxide film
6
as an inner-wall oxide film has to be reduced in thickness as the isolation spacing decreases.
FIGS. 21
to
24
are cross-sectional views illustrating a method of manufacturing a semiconductor device having a trench isolation structure with a thin inner-wall oxide film. The process steps shown in
FIGS. 21
to
24
correspond to those of
FIGS. 16
to
19
, respectively, but differ in that the thermal oxide film
6
is replaced with a thinner thermal oxide film
26
.
By forming in this way the thermal oxide film
26
which is thinner than the thermal oxide film
6
as an inner-wall oxide film on the trench
5
, polycrystalline silicon oxide areas
26
a,
which are formed by local oxidation of the polycrystalline silicon layer
3
during the formation of the thermal oxide film
26
, also become narrower than the polycrystalline silicon oxide areas
6
a
in the horizontal direction of the drawing.
Consequently, as shown in
FIG. 21
, the horizontal width of “bird's beak” formed of the thermal oxide films
4
,
26
, and
26
a
in trench-corner neighboring areas is reduced.
This lessens the effect of inhibiting the formation of recessing in the trench-corner neighboring areas during removal of the thermal oxide film
4
. Accordingly, recesses are formed in trench-corner neighboring areas
12
as shown in FIG.
23
and consequently, a thin gate oxide film
10
(
26
) is formed in trench-corner neighboring areas
13
as shown in FIG.
24
.
FIG. 25
is a graph showing the relationship between the threshold voltage and channel width of MOSFETs. As shown, ideally, the threshold voltage Vth should be constant irrespective of the channel width W as indicated by the channel-width dependency line L
1
, but in practice, a phenomenon, called the inverse narrow channel effect, occurs that the threshold voltage Vth decreases with decreasing channel width W as indicated by the channel-width dependency line L
2
.
As the inverse narrow channel effect becomes pronounced, a design margin for transistors decreases. Especially as device dimensions decrease, resultant variations in the threshold voltage Vth become more pronounced and the operating characteristics of the devices become more unstable.
One of the causes of the inverse narrow channel effect is a gate field eff

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