Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-21
2002-04-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S673000, C438S685000, C438S701000
Reexamination Certificate
active
06368959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device. Specifically, the present invention relates to a method of manufacturing a semiconductor device having a multilayer interconnection structure, wherein via hole contacts are formed.
2. Description of the Related Art
As to a multilayer interconnection used in a semiconductor device, a multilayer metal film comprised of a structure wherein an aluminum alloy film is sandwiched between high melting-point metal films such as a titanium (Ti) film, a titanium nitride (TiN) film, etc. or a structure sandwiched with a stacked or laminated film thereof has heretofore been used as interconnections for respective layers. When wiring layers for the respective layers are electrically connected to one another, they are electrically connected to one another by using plugs formed in via holes defined in an interlayer insulating film, e.g., tungsten (W) plugs as a typical example. The W plugs are formed in the following manner. A TiN film used as an adhesive layer is formed within the via holes defined in the interlayer insulating film by sputtering. Thereafter, a W film is formed so as to be fully embedded in the via holes by chemical vapor deposition (CVD) for reducing a tungsten hexafluoride (WF
6
) gas by a silane (SiH
4
) gas or hydrogen (H
2
) gas.
With respect to the formation of the W film, a nucleated layer of W is first formed with a thickness range of about 5 nm to 50 nm under the condition that the SiH
4
gas is heavily supplied. The resultant nucleated layer serves as a bed or primary film for growing the W film to a uniform film thickness. The formation of the W film under such a condition is rate-controlled according to the supply of the WF
6
gas. As a result, there is a tendency to form the W film so as to be thicker than other portions at ends of the via holes. Next, the W film for embedding the via holes therein is formed under the condition that the H
2
gas is heavily supplied. The formation of the W film under such a condition is rate-controlled by a reduction reaction of the WF
6
gas. As a result, the W film can be uniformly formed at any portion in the via holes. After the completion of the embedding of the via holes, the W film provided at locations other than the via holes is removed by etchback or CMP (Chemical Mechanical Polishing), so that W plugs are formed within the via holes respectively.
However, the conventional method of manufacturing the semiconductor device has encountered difficulties in ensuring a satisfactory device characteristic because it has the following problems. When the via hole is reduced in diameter with miniaturization of a device, the TiN film used as the adhesive layer is not sufficiently formed within each via hole. This results from the fact that the TiN film would be formed so as to become thicker than other portions at the via-hole ends. Since the TiN film is formed thick at the ends of the via holes, the via holes are reduced in diameter at their ends. Even if the uniform W film could be formed, voids remain within the via holes respectively.
Upon etchback, the etching rapidly progresses inside the via holes in which the voids exist thereinside, so that even a lower layer interconnection is overetched. Further, an oxidizing agent used upon CMP of the W film enters into the voids to thereby dissolve the W film. Furthermore, the etching of the voids in the via holes might progress in parallel with the etching of an upper layer interconnection in the case of a macro device in which sufficient alignment allowance cannot be set to the interconnection and via holes, so that a satisfactory device characteristic cannot be ensured.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of ensuring a satisfactory device characteristic.
According to one aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising:
successively forming a first insulating film, a first wiring layer and a second insulating film comprised of a laminated film of a single layer or two or more layers over a semiconductor substrate;
preparing a resist mask patterned over the second insulating film and successively effecting isotropic etching and anisotropic etching thereon to thereby define a plurality of via holes;
forming a high melting-point metal film so as to be sufficiently embedded in the plurality of via holes;
polishing the high melting-point metal film and the second insulating film until the high melting-point metal films formed within the plurality of via holes adjacent to each other are isolated from each other; and
forming a second wiring layer electrically connected to the first wiring layer through the high melting-point metal films formed within the plurality of via holes.
REFERENCES:
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5514622 (1996-05-01), Bornstein et al.
patent: 5726098 (1998-03-01), Tsuboi
patent: 5849618 (1998-12-01), Jeon
patent: 5872053 (1999-02-01), Smith
patent: 07201993 (1995-08-01), None
patent: 08222632 (1996-08-01), None
patent: 10-163207 (1998-06-01), None
patent: 10214834 (1998-08-01), None
patent: 11031745 (1999-02-01), None
Lee Calvin
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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