Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
1998-04-22
2001-05-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S513000, C438S597000, C438S618000, C438S478000, C257S298000, C257S052000, C427S099300
Reexamination Certificate
active
06228749
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device such as a capacitor element incorporated in a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device using an HSG (Hemi-Spherical-Grain) technique.
In the manufacture of dynamic random access memories (DRAMs) and the like, a higher integration degree has conventionally been required. To meet this requirement, an area necessary for each memory cell in the DRAM is greatly reduced. For example, in a 1- or 4-Mbit DRAM, a design rule using a minimum design width of 0.8 &mgr;m is employed; in a 16-Mbit DRAM, a design rule using a minimum design width of 0.6 &mgr;m is employed.
While the memory capacity increases in this manner, the semiconductor chip size cannot be increased in terms of high manufacturing efficiency and low cost. How to reduce a memory cell area is therefore an important theme in such semiconductor techniques.
A reduction in memory cell area results in a small charge storage amount. For this reason, it is becoming difficult to ensure a necessary charge amount of the memory cell along with an increase in integration degree of the memory cell. To solve this problem, memory cells having trench capacitors and stacked capacitors have conventionally been proposed and used in practical applications.
Of these memory cells, the memory cell having a stacked capacitor is advantageous in that its structure has high resistance to software errors and does not damage an Si substrate, compared to the structure of the memory cell having a trench capacitor. The memory cell structure having a stacked capacitor is expected as a next-generation memory cell structure.
The memory cell structure having a stacked capacitor is formed by an HSG technique in which a plurality of convexities are formed on the surface of a capacitor element to increase the charge storage amount.
The stacked capacitor is made up of a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is electrically connected through a contact hole formed in an interlevel insulating film to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a semiconductor substrate. In this case, many hemispherical grains are formed on the surface of a storage electrode operating as the lower electrode of the capacitor to substantially increase the surface area of the storage electrode and obtain a large capacitance.
Several types of HSG technique are available. Of these techniques, so-called nucleation of forming nuclei by irradiation of SiH
4
or the like on an amorphous silicon surface and forming convexities by annealing is proposed.
FIGS. 2A
to
2
C show the steps in manufacturing a capacitor element by a conventional nucleation method. As shown in
FIG. 2A
, after a capacitor contact hole
2
a
is formed in an Si oxide film
2
made of BPSG (BoroPhosphoSilicate Glass) or the like on an Si substrate
1
, doped amorphous silicon containing phosphorus at a concentration of 1E20 to 1E21 cm
−3
is grown and formed into a stack shape (to be referred to as an amorphous silicon stack hereinafter)
3
by lithography and etching.
As shown in
FIG. 2B
, after the amorphous silicon stack
3
is cleaned to remove a native oxide film formed on its surface, the obtained structure is heated to 570° C. in an HSG processing apparatus (not shown) and irradiated with disilane (Si
2
H
6
) at 1 mTorr for 40 sec to form nuclei
4
on the surface of the amorphous silicon stack
3
.
As shown in
FIG. 2C
, the obtained structure is annealed in a high vacuum at 570° C. for 2 min upon the irradiation of disilane, thereby forming hemispherical or mushroom-like HSG grains
7
on the surface of the amorphous silicon stack
3
. By the annealing, a crystallized layer
6
is internally grown from the surface of the amorphous silicon stack
3
, whereas a crystallized layer
5
is grown from the interface between the Si oxide film
2
and the amorphous silicon stack
3
.
If this annealing is continuously performed, the crystallized layer
5
may reach the crystallized layer
6
before the HSG grains
7
completely grow. Once the crystallized layer
5
reaches the crystallized layer
6
, subsequent HSG processing stops, and an ungrown portion
10
of the HSG grain
7
may be formed, as shown in FIG.
2
C.
For this reason, a method of suppressing the growth of the crystallized layer
5
by decreasing the annealing temperature has conventionally been adopted.
With a decrease in annealing temperature, however, the kinetic energy of Si atoms in the amorphous silicon surface decreases, and surface diffusion hardly occurs. As a result, the growth of HSG grains is also suppressed. In addition, since the temperature range optimal to the growth of HSG grains is narrow, the annealing temperature inside the HSG processing apparatus is difficult to uniformly control at high precision.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method of suppressing the growth of a crystallized layer. is another object of the present invention to provide a semiconductor device manufacturing method capable of efficiently forming convexities on an amorphous silicon surface.
In order to achieve the above objects, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming an amorphous silicon layer with a predetermined thickness to be electrically connected to a silicon substrate, on a silicon oxide film formed on the silicon substrate, forming a nucleus on a surface of the amorphous silicon layer by irradiation of a predetermined material while annealing the amorphous silicon layer at a first temperature, and forming a convexity on the surface of the amorphous silicon layer using the nucleus as a center while annealing the amorphous silicon layer having the nucleus at a second temperature lower than the first temperature.
REFERENCES:
patent: 5084413 (1992-01-01), Fujita et al.
patent: 5352291 (1994-10-01), Zhang et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5424244 (1995-06-01), Zhang et al.
patent: 5554566 (1996-09-01), Lur et al.
patent: 5854095 (1998-12-01), Kang et al.
patent: 5899725 (1999-05-01), Harshfield
patent: 5981974 (1999-11-01), Makita
patent: 6008101 (1999-12-01), Tanata et al.
patent: 2 313 477 (1997-11-01), None
patent: 2 313 231 (1997-11-01), None
patent: 2 314 683 (1998-01-01), None
patent: 5-304273 (1993-11-01), None
patent: 6-21390 (1994-01-01), None
patent: 8-306646 (1996-11-01), None
Lee Granville D
NEC Corporation
Smith Matthew
Sughrue Mion Zinn Macpeak & Seas, PLLC
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