Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1997-05-22

2001-05-01

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S424000, C438S226000, C438S426000, C438S296000

Reexamination Certificate

active

06225230

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a cell structure of, for example, a dynamic RAM (DRAM), particularly to a method of forming an element isolation insulating film by means of STI (Shallow Trench Isolation).
In recent years, prominent progress is being achieved in a large scale integration of semiconductor devices, particularly DRAM. In accordance with the progress, the area occupied by the unit memory element in the device tends to be markedly diminished. Also, it is unavoidable for the area occupied by the element isolation region to be diminished. Such being the situation, an STI method has come to be used as an element isolation method in place of the known LOCOS (Local Oxidation of Silicon) method.
A conventional STI method is proposed in, for example, B. Davari et al. “A New Planarization Technique Using a Combination of RIE and Chemical Mechanical Polish (CMP)”, IEDM, pp. 61-64, 1989.
FIGS. 1
,
2
A to
2
C,
3
A to
3
C and
4
accompanying the present specification collectively exemplify the conventional STI method proposed in this literature.
Specifically,
FIG. 1
is a cross sectional view showing that an insulating film
6
for element isolation is selectively formed in a surface region of a semiconductor substrate
1
. On the other hand,
FIGS. 2A
to
2
C and
3
A to
3
C collectively show the conventional STI method of forming the insulating film
6
.
As shown in
FIG. 2A
, a silicon oxide film
2
and a silicon nitride film
3
are formed in the first step on the surface of the semiconductor substrate
1
, followed by forming on the silicon nitride film
3
a resist layer
4
in a predetermined pattern by the known lithography method. In the next step, a reactive ion etching (RIE), which is an anisotropic etching method, is applied to the substrate
1
, with the resist layer
4
used as a mask, to form an element isolation region
5
in the semiconductor substrate
1
, as shown in FIG.
2
B. After formation of the element isolation region
5
, a silicon oxide-based insulating film
6
is deposited on the entire surface, as shown in FIG.
2
C. Further, a dummy pattern
7
is formed above the large element isolation region in order to moderate the surface irregularity taking place after deposition of the insulating film
6
.
In the next step, the entire surface is coated with a resist layer, followed by selectively removing the insulating film
6
and the dummy pattern
7
as well as the coated resist layer by RIE and the known CMP (Chemical Mechanical Polish) method, as shown in FIG.
3
A. In this step, the silicon nitride film
3
is used as an etching stopper, with the result that the surface of the substrate is flattened. Then, the silicon nitride film
3
is selectively removed by etching, as shown in FIG.
3
B.
Finally, a wet etching using a liquid etchant of HF or NH
4
F is applied to remove the silicon oxide film
2
, with the result that an STI is formed in the semiconductor substrate
1
, as shown in FIG.
3
C. In this wet etching step, the insulating film
6
is over-etched at the boundary region with the element region because the etching proceeds isotropically, as shown in FIG.
3
C.
In general, the insulating film
6
buried in a groove consists of silicon dioxide like the silicon oxide film
2
. Therefore, in the wet etching step, the insulating film
6
is partly removed together with the oxide film
2
, with the result that a concave portion
15
is formed at the edge of the groove.
Further, a gate insulating film
16
and a polycrystalline silicon layer
17
doped with phosphorus are formed in this order to form a laminate structure on the semiconductor substrate
1
having the STI formed thereon, as shown in FIG.
4
. As already described, the concave portion
15
is formed in the edge of the groove. It follows that the laminate structure consisting of the polycrystalline silicon layer
17
and the gate insulating film
16
has a thickness B in the concave portion
15
larger than a thickness A in the other portion.
Further, the polycrystalline silicon layer
17
is coated with a resist layer, followed by selectively applying an anisotropic etching such as RIE to the polycrystalline silicon layer
17
coated with the resist layer to form a striped gate electrode. Still further, an impurity is selectively implanted into the semiconductor substrate
1
so as to form diffusion regions (not shown) used as source and drain regions. In the anisotropic etching step, it is difficult to remove completely the thick polycrystalline silicon layer
17
deposited on the gate insulating film
16
. In other words, it is unavoidable for some portion of the polycrystalline silicon layer
17
to be left unremoved on the gate insulating film
16
. What should be noted is that the residual polycrystalline silicon layer causes a short-circuit problem between adjacent gate electrodes.
In addition, the conventional STI method requires a large number of treating steps, leading to a high cost and a low yield.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention, which has been achieved in view of the situation described above, is to provide an improved STI method which permits preventing a concave portion from being formed at an edge of an insulating film for an element isolation and also permits decreasing the treating steps so as to facilitate formation of the element isolation insulating film with a high yield.
In the method of the present invention, a groove is formed in a semiconductor substrate, followed by filling at least the groove with an insulating film. Then, a flattening treatment is applied at least once for removing the insulating film from the surface of the semiconductor substrate such that the insulating film is left unremoved within the groove. In the last flattening treatment, a mirror-polishing method is employed in place of the wet etching method which is generally employed.
Since the mirror-polishing method is employed in place of the wet etching method, the insulating film buried in the groove for the element isolation is not excessively removed, with the result that a concave portion in question is not formed in the case of employing the method of the present invention. Naturally, the problem of a residual polycrystalline silicon within the concave portion need not be worried about. It follows that the present invention permits eliminating the short-circuit problem inherent in the conventional STI method between adjacent gate electrodes. In addition, a wet etching treatment which requirs many treating steps is not employed in the present invention. In other words, the method of the present invention permits decreasing the number of treating steps, leading to an improved yield and to a further miniaturization of the semiconductor chip.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


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T. Park et al., A Very Simple Trench Isolation (VSTI) Technology with Chemo-Mechanically Polished (CMP) Substrate Si, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 121-122.
B. Davari, et al., “A New Planarization Technique Using a Combination of RIE and Chemical Mechanical Polish (CMP),” IEDM, pp. 3.4.1-3.4.4, 1989.

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