Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1997-11-12
2000-04-25
Utech, Benjamin
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438409, 438745, 438753, H01L 2176
Patent
active
060543639
ABSTRACT:
A method of manufacturing a semiconductor article comprises steps of preparing a first substrate including a silicon substrate having a porous silicon layer and a nonporous semiconductor layer arranged on the porous silicon layer, bonding the first substrate and a second substrate to produce a multilayer structure with the nonporous semiconductor layer located inside, separating the first and second substrates of the multilayer structure from each other along the porous silicon layer by heating the multilayer structure and removing the porous silicon layer remaining on the separated second substrate.
REFERENCES:
patent: 4816420 (1989-03-01), Bozler
patent: 5371037 (1994-12-01), Yonehara
patent: 5374564 (1994-12-01), Bruel
patent: 5405802 (1995-04-01), Yamagata et al.
patent: 5492859 (1996-02-01), Sakaguchi et al.
patent: 5750000 (1998-05-01), Yonehara et al.
patent: 5840616 (1998-11-01), Sakaguchi et al.
patent: 5856229 (1999-01-01), Sakaguchi et al.
K. Barla, "SOI Technology Using Buried Layers of Oxidized Porous Si", IEEE Circuits and Devices Magazine, Nov. 1987, pp. 11-15.
K. Imai, "A New Dielectric Isolation Method Using Porous Silicon", Solid-State Electronics, vol. 24, No. 2, Feb. 1, 1981, pp. 159-164.
Imai, "Crystalline Quality of Silicon Layer Formed by FIPOS Technology", J. Crystal Growth, vol. 63, No. 3, pp. 547-553 (1983).
Maszara, "Silicon-On-Insulator by Wafer Bonding: A Review", J. Electrochem. Soc., vol. 138, No. 1, pp. 341-347 (1991).
Harendt, "Silicon on Insulator Material by Wafer Bonding", J. Elect. Mater., vol. 20, No. 3, pp. 267-277 (1991).
Baumgart, "Light Scattering Topography Characterization of Bonded SOI Wafers", Extended Abstract of ECS First International Symposium of Wafer Bonding, pp. 375-385 (1991).
Hunt, "Thinning of Bonded Wafers: Etch-Stop Approaches", Extended Abstract of ECS First International Symposium of Wafer Bonding, pp. 165-173 (1991).
Yonehara, "Epitaxial layer transfer by bond and etch back of porous Si", Appl. Phys. Lett., vol. 64, No. 16, pp. 2108-2110 (1994).
Uhlir, "Electrolytic Shaping of Germanium and Silicon", Bell Syst. Tech. J., vol. 35, pp. 333-347 (1956).
Unagami, "Formation Mechanism of Porous Silicon Layer by Anodization in HF Solution", J. Electrochem. Soc., vol. 127, No. 2, pp. 476-483 (1980).
VanVeen, "Helium-Induced Porous Layer Formation in Silicon", Mat. Res. Soc. Symp. Proc., vol. 107, pp. 449-454 (1987).
Raineri, "Silicon-on-insulator produced by helium implantation and thermal oxidation", Appl. Phys. Lett., vol. 66, No. 26, pp. 3654-3656 (1995).
Atoji Tadashi
Sakaguchi Kiyofumi
Yonehara Takao
Canon Kabushiki Kaisha
Chen Kin-Chan
Utech Benjamin
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