Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-09
2011-08-09
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07994055
ABSTRACT:
A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire exposed through said via hole, on an inner wall of said via hole and on an inner wall of said wire trench, forming a seed layer on said underlying wire and on said diffusion barrier film formed on the inner wall of said via hole and the inner wall of said wire trench while concurrently said diffusion barrier film deposited on the bottom of said via hole is being etched, and forming metal wire in said via hole and in said wire trench.
REFERENCES:
patent: 7507666 (2009-03-01), Nakao et al.
patent: 2004/0188839 (2004-09-01), Ohtsuka et al.
patent: 2005/0218519 (2005-10-01), Koike et al.
patent: 2006/0125100 (2006-06-01), Arakawa
patent: 2007/0020931 (2007-01-01), Koura et al.
patent: 2008/0142974 (2008-06-01), Arakawa
patent: 2005-277390 (2005-10-01), None
“Proceedings of the International Interconnect Technology Conference,” IEEE Electron Devices Society; Jun. 6-8, 2005; San Francisco, California.
T. Usui et al, “Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer,” Semiconductor Technology Academic Research Center, Jun. 2005.
Chinese Office Action dated Aug. 21, 2009, issued in corresponding Chinese Patent Application No. 200810009253
Sakai Hisaya
Shimizu Noriyoshi
Fujitsu Semiconductor Limited
Garber Charles D
Stevenson Andre′ C
Westerman Hattori Daniels & Adrian LLP
LandOfFree
Method of manufacturing semiconductor apparatus, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor apparatus, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor apparatus, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2670547