Method of manufacturing MOS devices with reduced fringing...

Details Method of manufacturing MOS devices with reduced fringing... Method of manufacturing MOS devices with reduced fringing...

2007-05-15

2007-05-15

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S183000, C438S926000, C257SE21453

Reexamination Certificate

active

10897291

ABSTRACT:
An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 6025235 (2000-02-01), Krivokapic
patent: 6034401 (2000-03-01), Hsia et al.
patent: 6169315 (2001-01-01), Son
patent: 6316323 (2001-11-01), Fang et al.
patent: 6326272 (2001-12-01), Chan et al.
patent: 6392271 (2002-05-01), Alavi et al.
patent: 6624032 (2003-09-01), Alavi et al.
patent: 2002/0192911 (2002-12-01), Parke

Affiliated with

Also associated with

Rating

Method of manufacturing MOS devices with reduced fringing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing MOS devices with reduced fringing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing MOS devices with reduced fringing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3777197