Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2000-01-20
2001-05-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S306000
Reexamination Certificate
active
06235564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and, more particularly, to a method of manufacturing a MISFET having a gate electrode made of only metal.
2. Description of the Background Art
In recent years, there has been a demand for higher-speed operation and higher integration of semiconductor devices. Gate electrode patterns of MISFETs accordingly have been decreasing in size. However, the decrease in the size of the gate electrode patterns increases electric resistance. To solve this problem, a gate electrode made of a polycide constructed such that a compound film (silicide film) of high-melting-point metal such as tungsten with silicon is formed on a polysilicon film has been recently used in place of a gate electrode made of only polysilicon which has been historically dominant.
With further decrease in gate electrode pattern size, the polycide film cannot meet the requirement for sufficiently low electric resistance of the gate electrode. To overcome this problem, a structure such that a metal film, rather than the silicide film which is a compound, is formed on the polysilicon film has been under study (as disclosed, for example, in Japanese Patent Application Laid-Open No. P09-246543A (1997)).
For still further decrease in electric resistance of the gate electrode, it is desirable that the entire gate electrode is made of metal without using polysilicon.
It is contemplated that the gate electrode made of metal may be manufactured by a background art method to be described below. Initially, as shown in
FIG. 48
, a gate insulation film material
2
, a gate electrode material
11
which is metal and a photoresist
10
are formed on a surface of a semiconductor substrate
1
, and the photoresist
10
is patterned. Using the patterned photoresist
10
as a mask, etching is performed to shape the gate electrode material
11
into a gate electrode. Then, the photoresist
10
is removed, as shown in FIG.
49
. This completes a MIS gate structure.
However, the use of the above described background art manufacturing method presents a problem to be described below.
The gate electrode material
11
which is metal such as tungsten is often etched by dry etching using BCl
3
gas, SF
6
gas or the like. These gases contain boron and fluorine which are more reactive than oxygen and thus serve as a reductant. Thus, if a silicon oxide film or other oxygen-containing insulation films are used as the gate insulation film material
2
, boron and fluorine are prone to substitute for oxygen contained in the gate insulation film material
2
to combine with silicon. As a result, there is a likelihood that the etching of the gate electrode material
11
removes the gate insulation film material
2
and also the semiconductor substrate
1
. Thus, it is difficult to ensure an etch selectivity between the gate electrode material
11
and the gate insulation film material
2
.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of manufacturing a MISFET comprises the steps of: (a) preparing a semiconductor substrate; (b) forming a gate insulation film on a surface of the semiconductor substrate; (c) forming a dummy gate on a surface of the gate insulation film; (d) implanting an impurity into the semiconductor substrate in a self-aligned manner, using the dummy gate as a mask; (e) forming an interlayer insulation film to cover the surface of the semiconductor substrate entirely; (f) reducing the thickness of the interlayer insulation film to leave the interlayer insulation film only on a side of the dummy gate; (g) removing the dummy gate, with the interlayer insulation film and the gate insulation film left unremoved; and (h) forming a gate electrode in a space created by the removal of the dummy gate.
Preferably, according to a second aspect of the present invention, in the method of the first aspect, the gate insulation film, the dummy gate and the interlayer insulation film are made of respective materials capable of providing an etch selectivity between the gate insulation film and the dummy gate and an etch selectivity between the interlayer insulation film and the dummy gate; and the step (g) comprises the step of providing the etch selectivity between the gate insulation film and the dummy gate and the etch selectivity between the interlayer insulation film and the dummy gate to etch the dummy gate.
Preferably, according to a third aspect of the present invention, the method of the first aspect further comprises the step of (i) reducing a gate length of the dummy gate.
Preferably, according to a fourth aspect of the present invention, in the method of the third aspect, the gate insulation film, the dummy gate and the interlayer insulation film are made of respective materials capable of providing an etch selectivity between the gate insulation film and the dummy gate and an etch selectivity between the interlayer insulation film and the dummy gate. The step (g) comprises the step of providing the etch selectivity between the gate insulation film and the dummy gate and the etch selectivity between the interlayer insulation film and the dummy gate to etch the dummy gate. The step (i) comprises the step of providing the etch selectivity between the gate insulation film and the dummy gate to isotropically etch the dummy gate.
Preferably, according to a fifth aspect of the present invention, in the method of the third aspect, the dummy gate has an upper part and a lower part; and the gate length of only the lower part of the dummy gate is reduced in the step (i).
Preferably, according to a sixth aspect of the present invention, in the method of the fifth aspect, the gate insulation film, the upper part and the lower part of the dummy gate and the interlayer insulation film are made of respective materials capable of providing an etch selectivity between the gate insulation film and the lower part of the dummy gate, an etch selectivity between the lower part of the dummy gate and the upper part of the dummy gate, an etch selectivity between the upper part of the dummy gate and the interlayer insulation film, and an etch selectivity between the lower part of the dummy gate and the interlayer insulation film. The step (g) comprises the step of providing the etch selectivity between the gate insulation film and the lower part of the dummy gate, the etch selectivity between the upper part of the dummy gate and the interlayer insulation film and the etch selectivity between the lower part of the dummy gate and the interlayer insulation film to etch the upper and lower parts of the dummy gate. The step (i) comprises the step of providing the etch selectivity between the gate insulation film and the lower part of the dummy gate and the etch selectivity between the lower part of the dummy gate and the upper part of the dummy gate to isotropically etch the lower part of the dummy gate.
Preferably, according to a seventh aspect of the present invention, in the method of any one of the third to sixth aspects, the steps (d) and (i) are repeated a plurality of times before the step (e).
The use of the method according to the first aspect of the present invention eliminates the need to take into consideration an etch selectivity between the gate electrode material and the gate insulation film material to manufacture the MISFET including an all-metal gate electrode. The method according to the first aspect does not use a lift-off process to remove the interlayer insulation film overlying the dummy gate. This provides the dummy gate of a height equal to the thickness of the interlayer insulation film, eliminating the need to make the dummy gate higher than necessary. The presence of the gate insulation film prevents the semiconductor substrate from being damaged during the removal of the dummy gate.
The method according to the second aspect of the present invention provides the etch selectivity between the gate insulation film and the dummy g
Inoue Yasuo
Itoh Yasuyoshi
Oda Hidekazu
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Rocchegiani Renzo N.
Smith Matthew
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