Method of manufacturing metallic interconnect

Details Method of manufacturing metallic interconnect Method of manufacturing metallic interconnect

1998-05-15

2002-04-23

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S672000, C257S759000, C257S760000

Reexamination Certificate

active

06376359

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87104003, filed Mar. 18, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a metallic interconnect. More particularly, the present invention relates to a method of manufacturing a metallic interconnect that can produce a metallic layer having low internal stress.
2. Description of Related Art
As the level of integration for semiconductor devices continues to increase, more MOS transistors can be packed within a given wafer surface. As the number of transistors increases, the number of metallic interconnects required to connect them also rises correspondingly. Soon, wafer surface area will be insufficient for laying down all the necessary interconnects. Consequently, designs having two or more metallic layers have become a necessity for integrated circuit fabrication. Since these metallic layers must be separated from each other by an inter-metal dielectric layer to prevent short-circuiting, the properties and quality of the inter-metal dielectric layer are an important consideration.
At present, aluminum is the most commonly used conductive material in the fabrication of VLSI circuits. Aluminum has good electrical conductivity, is relatively cheap, is easy to deposit and etch, and has good adhesion with a silicon surface. Hence, aluminum is widely used as runners for connecting devices. However, as the level of integration of semiconductor devices continues to increase, many technical difficulties regarding the use of aluminum as a runner for devices are being encountered.
Conventionally, silicon dioxide (SiO
2
) is used as an inter-metal dielectric layer. However, aluminum is able to carry out the following chemical reaction with silicon dioxide at an aluminum/silicon dioxide interface:
4Al+3SiO
2
→2Al
2
O
3
+3Si
According to thermodynamics, aluminum oxide (Al
2
O
3
) is more stable than silicon dioxide (SiO
2
). Therefore, silicon dioxide and aluminum can easily inter-diffuse at an elevated temperature, replacing the silicon dioxide by aluminum oxide. In other words, spiking can easily occur at the aluminum/silicon dioxide interface.
Whenever aluminum and silicon dioxide interact chemically at the aluminum/silicon dioxide interface, there will be corresponding change in volume. From the above chemical formula, it can be easily shown that the volume occupied by aluminum (1.66×10
−23
cm
3
/atom) and silicon dioxide (4.3×10
−23
cm
3
/molecule) together is much larger than the volume of aluminum oxide (4.27×10
−23
cm
3
/molecule) and silicon (2×10
−23
cm
3
/atom) after the reaction. Therefore, due to the change in volume before and after the chemical reaction, lattice vacancies will be formed at the interface. The accumulation of these lattice vacancies will result in the formation of voids along, the aluminum lines, and may give rise to stress migration or thermal induced migration problems.
The continuous use of integrated circuits speeds up the growth of the above voids in the aluminum runners. Finally, at some point, some of the voids may grow large enough to join together, thereby opening the circuit. Therefore, functional failure or reliability problems may result.
FIGS. 1A and 1B
are cross-sectional views showing the progression of manufacturing steps in fabricating a conventional metallic interconnect. First, as shown in
FIG. 1A
, a metallic layer
12
made from aluminum or aluminum alloy is formed over a substrate
10
. A MOS device below the metallic layer
12
is not shown in FIG.
1
A. Next, a conformal oxide layer
14
is formed over the metallic layer
12
and the substrate
10
, and then a glass layer
16
having a good gap-filling capacity is spin-coated over the oxide layer
14
. The spin-coated glass layer
16
can be formed from silicate, siloxane or hydrogen silsesquoxane (HSQ) material. Thereafter, another oxide layer
18
, for example, a silicon dioxide layer having a pre-defined thickness, is deposited over the glass layer
16
and the oxide layer
14
. Next, as shown in
FIG. 1B
, the oxide layer
18
is planarized using, for example, a chemical-mechanical polishing method, thus obtaining a planar oxide layer
18
a
. Then, a metal plug
15
is formed, to act as an electrical connection between the metallic layer
12
and another subsequently formed metallic layer. After the above operations, the original oxide layers
18
and
14
now become oxide layers
18
a
and
14
a
. The oxide layer
18
a
, the spin-coated glass layer
16
and the oxide layer
14
a
together constitute an inter-metal dielectric layer. Finally, a metallic layer
13
made from aluminum or aluminum alloy is formed over the oxide layer
18
a.
In the manufacturing of metallic interconnects, lattice vacancies can easily form at the interface between the metallic layer
12
and the oxide layer
14
a
as well as the interface between the metallic layer
13
and the oxide layer
18
a
. Eventually, voids are formed in the metallic layers
12
and
13
, resulting in stress migration and thermal induced migration problems. Therefore, metallic runners can easily break causing an open circuit condition, which compromise the reliability of the devices.
In light of the foregoing, there is a need to improve the method of manufacturing metallic interconnects.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method of manufacturing metallic interconnects capable of producing a metallic layer having lower internal stress and higher device reliability.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing metallic interconnects. The method comprises the steps of forming a silicon-rich oxide layer both before and after the formation of a metallic layer. Therefore, the metallic layer is fully enclosed by silicon-rich oxide layer and any direct contact between the metallic layer and any silicon dioxide layer is avoided. Hence, lattice vacancies/voids that can lead to conventional stress migration and thermal induced migration problems are prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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