Method of manufacturing mask read-only memory cell

Details Method of manufacturing mask read-only memory cell Method of manufacturing mask read-only memory cell

2001-01-09

2002-05-21

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185260, C365S189011, C365S185010, C365S094000

Reexamination Certificate

active

06392930

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of manufacturing mask read-only memory (ROM) cell, and more particularly to a method of manufacturing a ROM cell from a fabrication of a dynamics random access memory (DRAM).
2. Description of the Related Art
Memory cells of a read-only memory (ROM) are generally made using channel transistors. Programming of the ROM is achieved by selectively implanting ions into the channels of these transistors. By implanting ions into the channel regions of specified transistors, threshold voltage of the devices changes. Hence, the “on” or “off” state of the memory cell is coded. A mask ROM cell is formed by laying a polysilicon word line (WL) over a bit line (BL), and the memory cell channel is formed in the region underneath the word line between neighboring bit lines. Normally, each ROM cell is in a logic state of “1” or “0” depending on whether ions are implanted into the channel region or not. The advantage of being able to program the state of each ROM cell by an ion implant operation is that semi-finished ROM products can be made. Once the required program codes arrive, a mask can be made and then the final ion implant operation can be carried out, thereby shortening customers' delivery date. However, the method requires the production of one more photomask to carry out an ion implant operation. Moreover, reliability of the final ROM product is very much dependent upon the quality of the ion implant operation.
An alternative method is to decide which channels are to be conductive prior to the production of the channel transistors. If a particular channel in a memory cell is designed to be non-conductive, a field oxide (FOX) layer is formed in the channel region of the transistor. Since the programming pattern is already established prior to production, no additional photomask and ion implant operation is need. Hence, higher reliability can be attained. However, as the level of device integration continues to increase, the available space for accommodating a memory cell decreases correspondingly. Because the edge of a FOX layer includes a bird's beak structure, the ultimate level of integration is affected. Moreover, the upper surface of a FOX layer is higher than the level of the surrounding substrate surface after thermal oxidation. Consequently, the substrate has a lower degree of surface planarity.
Programmable ROM is one kind of the ROM. A structure of the programmable ROM is like a structure of semi-finished ROM product, in which a metal line connects to each transistor of a memory cell array. There is a fuse between the metal line and the transistor. The fuse is burnt to short by a high current while programming a memory cell. The short of the fuse presents the memory cell is in a logic state as “1”. On the other hand, a memory cell is in a logic state as “o” when the fuse is ok.
DRAM is a kind of volatile memory. When a power supply is turn off, date stored in the DRAM would disappear. ROM is a kind of non-volatile memory. Date stored in the ROM would keep even when the power supply is turn off. The fabrication of DRAM and the fabrication of ROM are quite different. Requirements are also different so that it's complicated to forming ROM and DRAM on one chip.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a ROM cell. A DRAM structure is provided. A high voltage is applied to make a dielectric film between an upper electrode and a lower electrode of a capacitor is breakdown to store a logic date as “1”.
The DRAM cell comprises a capacitor. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of the capacitor. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell as a ROM cell is thus readout as a stock at fault to stock a logic state of “1” or “0”. The stored data as “1” or “0” is depended on voltage of the upper electrode (V
PL
) and a voltage of the bit line (V
BL
). If V
PL
>V
BL
, the breakdown of the dielectric film would make the cell stock at “1”, and a normal DRAM cell is stocked at “0”, and vice versa.


REFERENCES:
patent: 5768182 (1998-06-01), Hu et al.
patent: 5995409 (1999-11-01), Holland
patent: 6177703 (2001-01-01), Cunningham

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