Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1999-03-11
2000-12-05
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438699, 438700, 438702, 438706, 438745, H01L 21302
Patent
active
061566640
ABSTRACT:
A method of manufacturing a liner insulating layer for a node contact hole. A substrate having an first insulating layer formed thereon is provided, wherein the first insulating layer has a node contact hole penetrating through the first insulating layer and exposing the substrate. A protective layer is formed on the substrate exposed by the node contact hole. A liner insulating layer is formed on the first insulating layer and in the node contact hole. A second insulating layer is formed on a portion of the liner insulating layer formed on the sidewall of the node contact hole. A portion of the liner insulating layer uncovered by the second insulating layer is removed. The protective layer and the second insulating layer are removed.
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patent: 5677563 (1997-10-01), Cronin et al.
patent: 5731242 (1998-03-01), Parat et al.
patent: 5789316 (1998-08-01), Lu
Huang Jiawei
Tran Binh X
United Semiconductor Corp.
Utech Benjamin L.
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