Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-27
2002-11-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S594000, C438S476000, C438S786000
Reexamination Certificate
active
06479374
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for producing a circuit structure. More particularly, the present invention is concerned with a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, not only can the line-to-line capacitance in the circuit structure be lowered, but also a low resistance metal, such as copper or silver, can be used as a material for a circuit, so that it has become possible to produce an excellent circuit structure in which the delay in the transmission of the electric signal (this phenomenon is the so-called “interconnect delay”) is greatly suppressed, as compared to the case of the conventional circuit structures. Further, by the method of the present invention, it has become possible to produce such an excellent circuit structure with high efficiency.
The present invention is also concerned with a multilayer circuit board comprising the above-mentioned excellent circuit structure, and a semiconductor device comprising the above-mentioned excellent circuit structure.
2. Prior Art
Conventionally, as a material for an insulator layer used in a multilayer circuit of a semiconductor device, such as an LSI, a non-porous silicon oxide or a silicon oxide having incorporated therein a fluorine atom or an organic group has been used. However, the dielectric constants of such materials are high. In recent years, the density of the circuit in a semiconductor device, such as an LSI, has been increasing and, hence, the distance between the adjacent conductive paths of the circuit has been decreasing. Due to the decreased distance between the adjacent conductive paths of the circuit, the adjacent conductive paths function as a capacitor. In this case, when the dielectric constant of the insulator layer is high, a problem arises that the capacitance in the circuit becomes large, thereby leading to the delay in the transmittance of the electric signal through the circuit (i.e., interconnect delay). Therefore, in order to lower the dielectric constant of the insulator layer, it is attempted to use an insulator layer composed of a composite of a silicon oxide and an organic polymer, or a porous silicon oxide, i.e., a composite of a silicon oxide and air which has a dielectric constant of approximately 1.
In the future, when the density of the circuit of a semiconductor device, such as an LSI, has further increased, the importance of the alleviation of the interconnect delay would become much greater than that at present. Therefore, in addition to the lowering of the dielectric constant of the insulator layer, it also becomes necessary to use, as a material for a circuit, a low resistance metal represented by copper and silver instead of the conventionally used aluminum. However, in the conventional process for producing a circuit structure, it is difficult to use such a low resistance metal as a material for a circuit. The reason is as follows. The conventional process comprises: forming a metal layer on the entire surface of a substrate; forming, on the metal layer, a photoresist pattern (protective layer), which corresponds to the desired circuit pattern; removing the non-protected portions of the metal layer (i.e., the portions of the metal layer which are not covered by the photoresist pattern) by the conventional etching process, thereby forming a circuit on the substrate; and coating the circuit with an insulator layer. The above-mentioned conventional etching process utilizes a substance which is capable of forming a high vapor pressure compound with the metal used for forming the circuit. In such a conventional etching process, the protected portions of the metal layer, which are covered by the photoresist, are not eroded, and only the non-protected portions of the metal layer are converted into a high vapor pressure substance, so that the non-protected portions of the metal layer are selectively removed. However, when the metal layer is formed from a low resistance metal represented by copper and silver, such a low resistance metal cannot form a high vapor pressure compound, but forms only a low vapor pressure compound, so that the circuit cannot be formed by the conventional etching process. Therefore, in the conventional techniques, the above-mentioned low resistance metal cannot be used as a material for forming a circuit.
In order to solve the above-mentioned problems, the so-called “damascene process” has been proposed. The damascene process comprises: forming an insulator layer on a substrate; forming, in the insulator layer, a groove which defines a pattern for a circuit; forming a layer of a metal on the entire surface of the insulator layer, so that the groove is completely filled with the metal; removing the metal which is not present in the groove by etch back method utilizing a plasma or chemical mechanical polishing (CMP) method, so that the surfaces of the insulator layer and the surface of the metal layer (which functions as a circuit) are exposed (with respect to the damascene method, reference can be made to, for example, “International Electron Device Meeting Technical Digest” (1997), p. 773-776, and Unexamined Japanese Patent Application Laid-Open Specification No. 62-102543). Thus, in the damascene process, the formation of the circuit need not be conducted by the conventional etching method, but can be conducted by etch back method utilizing a plasma or chemical mechanical polishing (CMP) method. Therefore, in the damascene process, a low resistance metal, such as copper or silver, can be used as a material for the circuit.
Further, as well known in the art, when the damascene process is employed for the production of a multilayer circuit board comprising a laminate of a plurality of circuit structures, the number of steps required for the production is small, as compared to that in the conventional process. Therefore, the damascene process is very advantageous for reducing the production cost.
Specifically, in the production of a multilayer circuit board by a conventional method, the formation of a new (upper) circuit structure on a (lower) circuit structure which has been already formed is conducted by a process comprising the steps of: forming, on the lower circuit structure, an insulator layer for separating the lower circuit structure from the upper circuit structure to be formed; forming, in the insulator layer, a vertical through-hole for accommodating therein a vertical conductive path which electrically connects the lower circuit structure and the upper circuit structure to be formed; forming a vertical conductive path in the through-hole; and forming the upper circuit structure in the same manner as mentioned above in connection with the conventional process for producing a circuit structure.
By contrast, in the damascene process, after an insulator layer for separating the lower circuit structure from the upper circuit structure (to be formed) is formed on the lower circuit structure, the formation of the vertical through-hole for accommodating therein a vertical conductive path (which electrically connects the lower circuit structure and the upper circuit structure to be formed) and the formation (in the insulator layer separating the lower circuit structure from the upper circuit structure) of the groove wh
Doi Ichiro
Ioka Takaaki
Tanabe Tsuneaki
Anya Igwe U.
Asahi Kasei Kabushiki Kaisha
Smith Matthew
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