Method of manufacturing interconnect substrate

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S678000, C257SE21590, C257SE21487, C257SE21492

Reexamination Certificate

active

07488678

ABSTRACT:
A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.

REFERENCES:
patent: 6485831 (2002-11-01), Fukushima et al.
patent: 6680081 (2004-01-01), Fukushima et al.
patent: 2002/0142094 (2002-10-01), Fukushima et al.
patent: 10-065315 (1998-03-01), None
patent: 2005-223062 (2005-08-01), None
patent: 2005-223063 (2005-08-01), None
patent: 2005-223064 (2005-08-01), None
patent: 2005-223065 (2005-08-01), None
patent: 2005-286138 (2005-10-01), None
patent: 2005-286139 (2005-10-01), None
patent: 2006-265693 (2006-10-01), None

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