Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-11-02
2001-05-29
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S723000
Reexamination Certificate
active
06239034
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to the fabrication of dielectric layers for semiconductor devices and more particularly to a method for forming an inter-metal dielectric (IMD) layers using spin-on-glass (SOG) for sub-half-micron semiconductor devices.
2) Description of the Prior Art
Semiconductor elements are continuously being miniaturized in order to make circuits smaller, faster, and less expensive. However this miniaturization creates may challenges. High quality dielectric layers between conductive lines in semiconductor devices is a critical necessity for the submicron feature sized era in the manufacture of integrated circuits. These high quality dielectric layers are required over conductive lines, such as polysilicon gates on the substrate surface (e.g., interlevel dielectric) and such as metal lines over the substrate (e.g. interlevel dielectric). VLSI devices require miniaturization of interconnects, etc., interconnection spaces, resulting in increase in steps formed on the surface of a substrate. This is a particular problem when spacing between conductive lines is less than 0.15 &mgr;m.
The manufacturing requirements of intermetal dielectric layers in sub-half micron semiconductor devices include: (1) voidless fill of narrow trenches (gaps) between conductors (metal lines), (2) surface being planar for successful patterning and etching of the new blanket metal deposition, (3) stable with respect to water transport and (4) exhibiting a net compressive stress.
Practitioners have improved planarization methods. For example, U.S. Pat. No. 5,459,105 (Matsumura) describes a planarization method for IMD using PESiO2, O3-TEOS, SOG, etchback and PESiO2. Also, U.S. Pat. No. 5,482,900 (Yang) and U.S. Pat. No. 5,426,076 (Moghadan) show planarization methods. Product literature from Allied Signal Inc, Advance microelectronics materials, 3500 Garrett Drive, Santa Clara Calif. 9554-2827 (phone 408-562-0330), describe Accuspin® 418 Flowable SOP (X-18), and Accuglass T-11 Series SOG-(111, 211, 211).
However these methods can be further improved to meet the above mentioned requirements and overcome the above mentioned shortcomings.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an intermetal dielectric layer that includes spin-on-glass layers that fill gaps less than 0.15 &mgr;m between conductive lines and eliminates the poison via problem.
It is an object of the present invention to provide a method for fabricating an intermetal dielectric layer that allows the use of thick barrier layers over metal lines while filling gaps less than 0.15 &mgr;m and maintains a low dielectric constant to improve RC delay.
It is an object of the present invention to provide a method for fabrication an intermetal dielectric layer that includes an improved SOG process that provides superior gap filling properties as well as maintains a low dielectric constant.
To accomplish the above objectives, the present invention provides a method of manufacturing an interlevel dielectric layer for a semiconductor device. The method comprises forming spaced conductive lines
14
over a semiconductor structure including a substrate. Next, a first conformal silicon oxide layer is formed by PECVD-SiH
4
over the spaced conductive lines and over the semiconductor structure. The spaced conductive lines
14
coated with the barrier layer
16
having gaps
15
therebetween.
In an important step, a novel first spin-on-glass (SOG) layer
18
is formed over the first silicon oxide layer. It is critical that the invention's first spin-on-glass has a superior gap filling coverage and has the reflow property as heated at proper temperatures. After the reflow process, it is critical that the first SOG layer
18
does not remain over the metal lines but fills the valleys
15
between the metal lines. See
FIGS. 1 and 5B
. A reflow is performed by heating the first spin-on-glass layer so that all of first SOG layer
18
over the spaced metal lines
16
flows in to the gaps between the metal lines.
Subsequently, a second silicon oxide layer
24
is preferably deposited using a plasma enhanced chemical vapor deposition (PECVD)-SiH
4
process over the first silicon oxide layer
16
and over the first spin-on-glass layer
18
in the gaps
15
. A second spin-on-glass layer
28
(“Planarizing” SOG) is then formed over the second silicon oxide layer
24
. An etchback is performed by etching back and removing the entire second spin on glass layer and portions the second silicon oxide layer. Lastly, an insulating cap layer
30
is formed over the second silicon oxide layer. The insulating cap layer formed of silicon oxide and silicon nitride.
The invention has the following key features:
A key feature of the invention is the novel 1st SOG layer
18
that has reflow properties so that the SOG fills gaps between metal lines >0.15 &mgr;m. Only traces of or No 1st SOG layer
18
remains above the metal lines
15
after reflow. See FIG.
1
.
The Invention's 1st SOG layer
18
is a new use specifically for Allied Signal Accuspin 418 SOP and HSG-2209S-R7 organic spin-on-glasses.
The first
18
and second SOG layers
28
have different coating functions and properties. The first SOG layer fills tight (>or equal to 0.1 &mgr;m) gaps
15
in between the metal lines
14
, and does not remain on top of the metal lines
14
. The second SOG layer is a “planarizing “sacrificial layer for etch back planarization. The second SOG layer does not have the reflow property of the first SOG layer.
The second SOG layer
28
is removed in an etched back to planarized the underlying SiO
2
layer
24
.
The present invention provides an improved interlevel (or intermetal) dielectric layer. The present invention provides an intermetal dielectric layer
16
18
24
30
that allows the use of thick barrier layers
16
over metal lines
14
while filling gaps
15
less than 0.15 &mgr;m. The excellent gap filling properties of the novel first SOG layer
18
allow the gaps to be filled without thinning the barrier layers
16
. The first SOG layer
18
maintains a low dielectric constant to improve RC delay. Moreover, by removing the entire 2nd spin-on-glass layer
28
over the via, the poison via problem is eliminated.
REFERENCES:
patent: 5110763 (1992-05-01), Matsumoto
patent: 5332694 (1994-07-01), Suzuki
patent: 5426076 (1995-06-01), Moghadam
patent: 5459105 (1995-10-01), Matsuura
patent: 5482900 (1996-01-01), Yang
patent: 5798298 (1998-08-01), Yang et al.
patent: 5883001 (1999-03-01), Jin et al.
patent: 5960321 (1999-09-01), Hsieh et al.
“Accuglass T-11 Series Spin-On Glass (SOG)” Allied Signal, Inc. Advance Microelectronics Materials, 3500 Garrett Dr. Santa Clara, CA, 9554-2827.
Chang Liang-Tung
Yang Fu-Liang
Ackerman Stephen B.
Deo Duy-Vu
Saile George O.
Staffel William J.
Utech Benjamin L.
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