Method of manufacturing integrated semiconductor circuit devices

Details Method of manufacturing integrated semiconductor circuit devices Method of manufacturing integrated semiconductor circuit devices

1984-08-08

1986-04-15

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576W, 29580, 148175, 148187, 156646, 156648, 156649, 156653, 156657, 1566591, 156662, 357 47, 357 59, 427 93, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

045825653

ABSTRACT:
A method of fabricating integrated semiconductor circuit devices with improved surface planarity. An oxidation-resistant masking layer is deposited over the surface of a semiconductor body and the walls of vertical trenches of a given width formed in the semiconductor body surface. The masking layer is removed in part from predetermined portions of the semiconductor body surface. A polycrystalline semiconductor material is deposited over the semiconductor body surface to bury the trenches, followed by continuous partial removal of the polycrystalline semiconductor material and the semiconductor body at portions corresponding to the predetermined portions of the semiconductor body surface to a predetermined surface level lower than the semiconductor body surface. The remainder of each of the polycrystalline semiconductor material and the above corresponding portions of the semiconductor body is thermally oxidized to present substantially the same surface level with the semiconductor body surface, whereby the semiconductor body has a flat surface. Preferably, a second oxidation-resistant masking layer is deposited over the partly removed semiconductor body along its whole surface including predetermined lower surface portions thereof in a manner superimposed upon the first-mentioned masking layer. The second masking layer is removed at portions on a predetermined level lower than the semiconductor body surface. Also portions of the semiconductor body from which the second masking layer has been removed are thermally oxidized during the above oxidation step, to further enhance the surface planarity of the semiconductor body.

REFERENCES:
patent: 4333227 (1982-06-01), Horng et al.
patent: 4473598 (1984-09-01), Ephrath et al.
patent: 4493740 (1985-01-01), Komeda

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