Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-10-25
2005-10-25
Guerrero, Maria F. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S669000, C438S942000, C438S945000, C438S948000, C438S950000
Reexamination Certificate
active
06958292
ABSTRACT:
In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1is used which is provided partially with light shielding patterns3aformed of a resist film, in addition to light shielding patterns formed of a metal.
REFERENCES:
patent: 4684971 (1987-08-01), Payne
patent: 5376483 (1994-12-01), Rolfson
patent: 5378585 (1995-01-01), Watanabe
patent: 5389474 (1995-02-01), Iguchi et al.
patent: 5418092 (1995-05-01), Okamoto
patent: 5538816 (1996-07-01), Hashimoto et al.
patent: 5556724 (1996-09-01), Tarumoto et al.
patent: 5738959 (1998-04-01), Miyashita et al.
patent: 5741613 (1998-04-01), Moon et al.
patent: 5948572 (1999-09-01), Liu et al.
patent: 5989760 (1999-11-01), Mangat et al.
patent: 6458496 (2002-10-01), Motonaga et al.
patent: 6511778 (2003-01-01), Okazaki et al.
patent: 6558855 (2003-05-01), Tanaka et al.
patent: 6596656 (2003-07-01), Tanaka et al.
patent: 6645856 (2003-11-01), Tanaka et al.
patent: 6677107 (2004-01-01), Hasegawa et al.
patent: 2003/0180670 (2003-09-01), Hasegawa et al.
patent: 54-21272 (1979-02-01), None
patent: 54-83377 (1979-07-01), None
patent: 55-22864 (1980-02-01), None
patent: 56-30129 (1981-03-01), None
patent: 59-22050 (1984-02-01), None
patent: 60-85525 (1985-05-01), None
patent: 63-274156 (1988-11-01), None
patent: 4-97254 (1992-03-01), None
patent: 4-136854 (1992-05-01), None
patent: 5-289307 (1993-11-01), None
patent: 7-325383 (1995-12-01), None
patent: 2000-21754 (2000-01-01), None
Hasegawa Norio
Miyazaki Ko
Mori Kazutaka
Okada Joji
Tanaka Toshihiko
Antonelli Terry Stout & Kraus LLP
Guerrero Maria F.
Renesas Technology Corp.
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