Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-10-24
2006-10-24
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S649000, C438S583000, C438S651000, C257S368000, C257S383000, C257S384000, C257S385000, C257S387000
Reexamination Certificate
active
07125787
ABSTRACT:
A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer8superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2of the gate electrode10on the second gate oxide films6A and6B is thinner than the thickness t1of the prior art. Therefore, the height gap h2between the gate electrode10and the N+type source layer11and the height gap h2between the gate electrode10and the N+type drain layer12become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film13.
REFERENCES:
patent: 5017979 (1991-05-01), Fujii et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5200637 (1993-04-01), Matsuo et al.
patent: 5346587 (1994-09-01), Doan et al.
patent: 5397909 (1995-03-01), Moslehi
patent: 5753954 (1998-05-01), Chi et al.
patent: 5882994 (1999-03-01), Araki et al.
patent: 5897365 (1999-04-01), Matsubara
patent: 6093950 (2000-07-01), Kuroda
patent: 6188113 (2001-02-01), Derhocobian et al.
patent: 5-259451 (1993-10-01), None
patent: 10-27857 (1996-07-01), None
patent: 10-335641 (1997-05-01), None
patent: 2000-49113 (2000-02-01), None
Andoh Wataru
Hirata Koichi
Momen Masaaki
Sekikawa Nobuyuki
Morrison & Foerster / LLP
Pham Long
Rao Shrininvas H.
Sanyo Electric Co,. Ltd.
LandOfFree
Method of manufacturing insulated gate semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing insulated gate semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing insulated gate semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3714522