Method of manufacturing gate structure

Details Method of manufacturing gate structure Method of manufacturing gate structure

2000-03-29

2001-06-19

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

Reexamination Certificate

active

06248653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a gate structure having a transistor, and particularly, to a gate electrode of a transistor.
2. Description of the Background Art
A conventional method of manufacturing a gate structure is described below by referring to
FIGS. 11
to
16
.
Referring to
FIG. 11
, a gate oxide film
2
and polysilicon
3
are formed on a semiconductor substrate
1
.
Referring to
FIG. 12
, masks (not shown) are applied to the regions where a Nch transistor and a Pch transistor will be formed respectively, followed by implantation of impurity. The impurity implanted to the polysilicon
3
is, for example, boron (B) in forming a Pch transistor, and phosphorus (P) in forming a Nch transistor. Then, a tungsten silicide (WSi)
4
is formed on the polysilicon
3
, and a silicon nitride film (SiN)
5
is formed thereon, as an upper mask.
Referring to
FIG. 13
, a resist (not shown) is formed, and the resist is patterned by photolithography technique. By using the resultant resist as a mask, the silicon nitride film
5
is etched away. By using the remaining silicon nitride film
5
as a mask, the gate oxide film
2
, polysilicon
3
and tungsten silicide
4
are etched away.
Referring to
FIG. 14
, masking with the gate oxide film
2
, polysilicon
3
and tungsten silicide
4
, impurity is implanted to the semiconductor substrate
1
, thereby forming a diffused layer
6
.
Referring to
FIG. 15
, the structure of
FIG. 14
is oxidized in an atmosphere of 100% oxygen, alternatively, an atmosphere of oxygen which is diluted with an inert gas, such as a nitrogen gas or argon. Thereby, an oxide film
7
is formed on the sidewalls of the polysilicon
3
and tungsten silicide
4
, and an oxide film
8
is formed on the surface of the diffused layer
6
of the semiconductor substrate
1
.
Referring to
FIG. 16
, a silicon nitride film is deposited on the structure of
FIG. 15
, following by etching for framing, thereby to leave the silicon nitride film as a sidewall layer
9
. Then, implantation for source/drain is conducted to form source/drain region
10
.
The resultant MOS transistor is shown in FIG.
16
. The polysilicon
3
and tungsten silicide
4
which are part of the gate electrode are referred to as a W (tungsten) polycide structure. The gate oxide film
2
, polysilicon
3
and tungsten silicide
4
constitute a gate electrode
400
a.
Meanwhile, the tendency toward scale down and high integration is enhanced, and a higher speed operation of circuits is demanded. To satisfy this demand, it has been considered to decrease the resistance of the gate electrode
400
a
of the MOS transistor.
In order to decrease the resistance of the gate electrode
400
a
, there are the following two manners: (I) to increase the film thickness of the tungsten silicide
4
; and (II) to employ metal, e.g., tungsten (W), which has a lower resistivity than the tungsten silicide
4
.
Unfortunately, with the manner (I), the gate electrode
400
a
is made high and slender in a direction vertically of the semiconductor substrate
1
. As a result, it is liable to fall, and there is difficulties encountered in burying an interlayer film between adjacent gate electrodes
400
a.
On the other hand, with the manner (II), there is the advantage that it is unnecessary to increase the height of the gate electrode
400
a
in order to decrease its resistance. However, due to the oxidation for forming the oxide films
7
and
8
in
FIG. 15
, the oxidation proceeds to the interior of metal, which causes peeling and increases the resistance of the gate electrode
400
a.
It can also be considered to omit the oxidation for forming the oxide films
7
and
8
, which causes an increase in the resistance of the gate electrode
400
a
. However, without this oxidation, oxide films
7
and
8
are not formed, so that the sidewall layer
9
and the diffused layer
6
of the semiconductor substrate
1
are brought into contact. When the sidewall layer
9
makes contact with the diffused layer
6
, due to the stress applied between the sidewall layer
9
and the diffused layer
6
of the semiconductor substrate
1
, a level occurs at the interface, and this level functions as a carrier trap, resulting in poor tolerance to hot carrier. Alternatively, it can be considered to carry out oxidation such that the oxidation does not proceed to the interior of metal. For instance, when oxidation is conducted at a high temperature, 1000° C. in an atmosphere of a mixed gas of hydrogen and oxygen which contains about 5% oxygen, metal is not oxidized, and only the sidewall of the polysilicon
3
and the surface of the semiconductor substrate
1
are oxidized. It is however necessary to add a new equipment for performing such a selective oxidation.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method of manufacturing a gate structure comprises the steps of: (a) forming a conductor through a gate insulating film, on a semiconductor substrate; (b) forming a first oxide film on the conductor; (c) oxidizing the sidewall of the conductor; (d) forming a second oxide film so as to cover the first oxide film; (e) performing planarization process from the second oxide film side of the semiconductor substrate, thereby to expose the first oxide film; (f) performing, to the structure obtained by the step (c), an etching process using a vapor phase hydrofluoric acid, thereby to selectively remove the first oxide film; and (g) forming a metal film in the region surrounded by the second oxide film and the conductor.
According to a second aspect, the above method further comprises the step (h), subsequent to the step (d) and prior to the step (e), of forming an insulating film having a lower etching rate than the second oxide film in the planarization process.
According to a third aspect, the first oxide film has an impurity concentration of 2% or more.
With the first aspect, the formation of the metal film in the region from which the first oxide film has been removed, enables to provide a gate structure of a low resistance, and therefore to suppress its height.
With the second aspect, the planarization process in the step (e) can be easily controlled.
With the third aspect, the selective removal of the first oxide film is attainable by the etching process using a vapor phase hydrofluoric acid in the step (f).
An object of the present invention is to provide a method of manufacturing a gate structure which enables to obtain a gate structure of a low resistance without increasing the height of the gate structure, and therefore to suppress its height.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5594264 (1997-01-01), Shirahata et al.
patent: 6018185 (2000-01-01), Mitani et al.
patent: 8-264531 (1996-10-01), None
patent: 9-246543 (1997-09-01), None

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