Method of manufacturing flash memory

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Reexamination Certificate

active

06521526

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory. More particularly, the invention relates to a method of manufacturing a flash memory capable of preventing oxidization of a given portion of WSix due to exposed WSix, in a way that a protection layer of doped amorphous silicon or amorphous silicon is formed on a semiconductor substrate in which a control gate is formed in a stack structure of doped poly Si and only a given portion of the protection layer is then etched in a subsequent process to form a contact hole.
2. Description of the Prior Art
Recently, a commercial flash device mainly includes a structure in which a control gate is formed in a stack structure of doped poly Si and WSix, an metal line and a contact plug for connecting the control gate and the metal line in order to give a device operating voltage are formed.
Explaining in short a method of manufacturing a flash device, a non-reflection layer and an insulating layer are sequentially deposited on a semiconductor substrate in which a control gate is formed in a stack structure of doped poly Si and WSix. The non-reflection layer and the insulating layer are then patterned by a given etching process to form a contact hole through which Wsix can be exposed. Thereafter, after an anti-diffusion film is formed on the entire structure including the contact hole, the contact hole is filled with tungsten plug. Then, a metal line and a barrier layer are sequentially deposited on the entire structure and are then patterned.
Upon formation of the contact hole, however, a given portion on an upper surface of WSix is exposed to oxygen by a given etching process. Then, the exposed portion of WSix and oxygen react to produce tungsten oxide such as WO
3
or WO on an upper surface of WSix. That is, as shown in
FIG. 1
, upon formation of the contact hole, tungsten oxide is formed between the anti-diffusion film and the WSix layer by means of given etching process.
The thickness of tungsten oxide is increased by means of a subsequent process so that tungsten oxide remains between WSix and the anti-diffusion film. Thus, there is a problem that a contact resistance between WSix ad the anti-diffusion film is increased to reduce the operating speed of the device.
Further, as shown in
FIG. 2
, in a higher-integrated flash device of 0.18 &mgr;m, a seam is generated within WSix, which causes to increase Rs of the control gate. The seam is a result of weaken growth interface of WSix exposed to oxygen during a high temperature oxide film formation process for supplementing a cell side wall since portions where different crystal directions meet by the difference of WSix deposition direction (or crystal growth direction) depending on the morphology after forming WSix. Thus, there is a problem that short of the control gate is caused.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a flash memory capable of preventing exposure of a given portion of a control gate, when a contact hole in which a contact plug will be formed is formed.
Another object of the present invention is to provide a method of manufacturing a flash memory capable of preventing exposure of a given portion of a control gate, in a way that the protection layer of doped amorphous silicon or amorphous silicon is formed on a semiconductor substrate in which a control gate is formed in a stack structure of doped poly Si and only a given portion of the protection layer is then etched in a subsequent process to form a contact hole.
In order to accomplish the above object, a method of manufacturing a flash memory according to the present invention, is characterized in that it comprises the steps of forming a control gate on semiconductor substrate in which given structures are formed; forming a protection layer on the control gate; forming a non-reflection layer on the protection layer; forming an insulating layer on the non-reflection layer; forming a contact hole to expose a given portion of the protection layer; forming a first metal protection film on the entire structure including the contact hole; forming a contact plug to fill the contact hole; forming a second metal protection film on the contact plug; and forming a metal line on the entire structure including an ohmic contact layer.


REFERENCES:
patent: 5607873 (1997-03-01), Chen et al.
patent: 5783471 (1998-07-01), Chu
patent: 5814862 (1998-09-01), Sung et al.
patent: 5973374 (1999-10-01), Longcor
patent: 6051467 (2000-04-01), Chan et al.
patent: 6143648 (2000-11-01), Rodriguez et al.

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