Method of manufacturing extended drain resurf lateral DMOS devic

Details Method of manufacturing extended drain resurf lateral DMOS devic Method of manufacturing extended drain resurf lateral DMOS devic

1995-02-16

1996-04-30

Thomas, Tom

Fishing, trapping, and vermin destroying

437 29, 437 30, 437 40, 437154, 148DIG126, H01L 21336, H01L 21266

Patent

active

055124950

ABSTRACT:
A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.

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