Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
2001-06-20
2004-12-28
Norton, Nadine G. (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
active
06835245
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a silicon single crystal, which is suited for use in the manufacture of a semiconductor integrated circuit device, by the Czochralski method and to a method of manufacturing an epitaxial wafer from the silicon crystal produced by that method. More particularly, it relates to a method of manufacturing an epitaxial wafer exhibiting high gettering capability while scarcely giving rise to stacking faults, dislocations and other defects in an epitaxial layer (hereinafter collectively referred to as “epitaxial layer defects”) when it is grown on a wafer obtained from a silicon single crystal produced with or without doping with nitrogen, and to a method of producing such a single crystal to serve as a raw material for the epitaxial wafer.
DESCRIPTION OF THE PRIOR ART
With the recent increase in the integration density of silicon semiconductor devices, quality requirements imposed on silicon wafers on which devices are formed have become more and more severe. For example, severer limitations are imposed than ever on dislocations and like crystal defects and/or metal impurities in the so-called “device active region” where devices are formed, with the increasing fineness of circuits as resulting from the increase in integration density, since such defects and impurities increase the leakage current and shorten the life of a carrier.
In the art, wafers prepared by slicing silicon single crystals produced by the Czochralski method are used for forming semiconductor devices thereon. These wafers generally contain about 10
18
atoms/cm
3
of supersaturation oxygen. Due to the thermal history in the steps of device formation, such oxygen forms oxide precipitate nuclei and thereby induces crystal defects such as dislocations and stacking faults. In the process of device manufacture, however, the so-called DZ layer (denuded zone) which is free of crystal defects and has a thickness of about tens of micrometers is formed near the wafer surface by diffusion of oxygen to the outside when the wafer is maintained at about 1100° C. for several hours in the step of field oxide film formation by LOCOS (local oxidation of silicon) or well diffusion layer formation. The DZ layer serves as a device active region, so that the occurrence of crystal defects is spontaneously prevented.
However, with the increase in the integration density of semiconductor devices, the high-energy ion implantation technique has been introduced for well formation by which the device process is carried out at a low temperature of 1000° C. or less. At such a temperature, the above-mentioned outward diffusion of oxygen does not occur to a sufficient extent, hence the DZ layer formation near the surface becomes insufficient. Therefore, attempts have been made to reduce the oxygen content in wafers, but such attempts have been unsuccessful in perfectly suppressing the formation of crystal defects.
Under such circumstances, epitaxial wafers having an epitaxial layer substantially free of crystal defects as formed therein have been developed and are now widely used in the manufacture of highly integrated devices. However, even epitaxial wafers high in crystallinity are used, the device characteristics are degraded due to contamination of the epitaxial layer with metal impurities in the subsequent device process steps.
The opportunity and influences of such contamination with impurity metal elements increase since the process becomes more complicated with the increase in the integration density. The contamination may be eliminated basically by cleaning the process environment and materials used. However, it is difficult to render the device process completely free of contaminants, hence the gettering technology becomes necessary as a measure for solving that problem. This is a means for entrapping contaminant impurity elements in a region (sink) other than the device active region to thereby render the contaminants harmless.
The gettering technology includes intrinsic gettering (hereinafter referred to as “IG” for short) which comprises entrapping impurity elements by utilizing oxygen-caused oxide precipitates spontaneously induced during heat treatment in the device process steps. However, when a wafer is heat-treated at a temperature as high as 1050-1200° C. in the epitaxial step, oxide precipitate nuclei occurring within the wafer sliced from a silicon single crystal shrink and vanish, whereby it becomes difficult to sufficiently induce oxide precipitates to serve as gettering sources within the wafer in the subsequent device process steps. Thus, even if the gettering technology is applied, a problem arises that any satisfactory IG effect cannot be exerted on metal impurities throughout the whole process.
To overcome such a problem, there is a proposal in the art that the wafer be heat-treated at 600-900° C. prior to the epitaxial step in the device manufacture to thereby allow oxide precipitate nuclei to grow to such a size that they hardly vanish even upon high temperature treatment in the epitaxial step (cf. e.g. Japanese Patent Application Laid-Open (Kokai) No. H08-339024).
Specifically, according to the proposal, oxide precipitate nuclei in the crystal are increased in size by heat treatment prior to device treatment to thereby increase the thermal stability thereof to a sufficient level. Even when the wafer is thereafter subjected to a high temperature heat treatment in the epitaxial step, the oxide precipitate nuclei will not shrink or vanish. The oxide precipitate nuclei that have survived the epitaxial step form oxide precipitates from the early stages of the device step and thus effectively serve as sinks for gettering, so that an excellent gettering effect can allegedly be expected. However, the proposed method has a problem in that the above heat treatment is required as a new process step in the silicon wafer manufacturing process and increases the cost of production of epitaxial wafers.
In addition to the above measure, methods of producing silicon single crystals have been proposed in the art which comprise doping the single crystals with nitrogen while they are grown by the Czochralski method, to thereby induce formation, within wafers, of oxide precipitate nuclei hardly vanishing even upon high temperature heat treatment in the epitaxial step (cf. e.g. Japanese Patent Application Laid-Open (Kokai) No. H11-189493 and Japanese Patent Application Laid-Open (Kokai) No. 2000-44389).
According to the methods proposed, a silicon single crystal having oxide precipitate nuclei which hardly shrink or vanish can be obtained even in the epitaxial step by increasing the thermal stability of oxide precipitate nuclei in the crystal by doping it with nitrogen while growing it by the Czochralski method. It is alleged that oxide precipitate nuclei remaining in wafers sliced from such single crystal after the epitaxial step form oxide precipitates from the early stages of the device step and thus effectively serve as sinks for gettering, so that the effects of IG can be expected from the early stages of the device step.
Later investigations, however, have revealed that high concentration nitrogen doping, for example doping with nitrogen at a concentration not lower than 1×10
14
atoms/cm
3
results in the formation of oxide precipitate nuclei, which are thermally stable and will not vanish even upon high temperature heat treatment in the epitaxial step, in the wafer inside and near the wafer surface as well and, therefore, in the epitaxial step, stacking faults, dislocations and the like occur in the epitaxial layer with the thermally stably oxide precipitate nuclei formed near the wafer surface serving as origins, readily inducing epitaxial defects. The epitaxial defects cause an increase in the leakage current and degradation in the gate oxide integrity, among others.
On the other hand, when nitrogen doping is effected at a low concentration, for example at 5×10
13
nitrogen atoms/cm
3
or below, the problem of epitaxial defects develop
Asayama Eiichi
Horai Masataka
Nishikawa Hideshi
Ono Toshiaki
Tanaka Tadami
Anderson Matthew A.
Norton Nadine G.
Sumitomo Mitsubishi Silicon Corporation
Westerman Hattori Daniels & Adrian LLP
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