Method of manufacturing electronic device

Details Method of manufacturing electronic device Method of manufacturing electronic device

2005-08-30

2005-08-30

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06938238

ABSTRACT:
In a method of forming a circuit pattern including fine pattern features and fine space, a hard mask layer is patterned with a first pattern defined by eliminating the fine space for merging the pattern features. Thereafter the hard mask layer is shrank. Next, the hard mask layer is patterned with a second pattern that is defined on the basis of the fine space. Finally, the circuit pattern is formed in an underlying layer using the hard mask layer as a mask.

REFERENCES:
patent: 6221567 (2001-04-01), Beilin et al.
patent: 6500756 (2002-12-01), Bell et al.
patent: 2001-308076 (2001-11-01), None
M. Neisser, et al., Proc. of SPIE, vol. 3334, pp. 372-383, “Simulation and Experimental Evaluation of Double Exposure Techniques”, 1998.
A. Yamaguchi, et al., Proc. of SPIE, vol. 4345, pp. 655-664, “AR Ion Implantation into Resist for Etching Resistance Improvement”, 2001.

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