Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-12
2001-10-16
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S631000, C438S633000, C438S926000
Reexamination Certificate
active
06303484
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing dummy patterns. More particularly, the present invention relates to a method of forming dummy patterns and spacers of a gate structure, simultaneously.
2. Description of the Related Art
Planarization is very important in ULSI technology. It can provide a smooth surface to ensure good metal step coverage and to provide a flat-enough field so that, within the lithography depth of focus, contact vias and metal wires can be patterned.
A true global planarization can be achieved by chemical/mechanical polishing (CMP) of an inter-layer dielectric (ILD).
FIGS. 1A
to
1
E show cross-sectional views of the conventional processes of CMP. Referring to
FIG. 1A
, polysilicon patterns
102
a
,
102
b
, and
102
c
are formed on the substrate
100
. As shown in
FIG. 1A
, the poly patterns
102
a
,
102
b
,
102
c
are densely arranged in region
101
a
, in what is called a dense region. In contrast, the region
101
b is an open area called sparse region.
Referring to
FIG. 1B
, an oxide layer
104
is formed on the substrate
100
and covers the poly patterns
102
a
,
102
b
, and
102
c.
Referring to
FIG. 1C
, the oxide layer
104
is etched back to form spacers
104
a
,
104
b
, and
104
c.
Referring to
FIG. 1D
, an ILD layer
106
is blanket-formed over the entire surface of substrate
100
, which surface includes both the dense region
101
a
and the sparse region
101
b
. As shown in
FIG. 1D
, the poly patterns cause a rough topography on the surface of ILD layer
106
.
Referring to
FIG. 1E
, the surface topography of the ILD layer
106
caused by previously formed polysilicon can be smoothed by polishing the ILD layer
106
with CMP.
However, the dense region
101
a
and sparse region
101
b
have different device densities. Therefore, as shown as
FIG. 1E
, the two regions have different polishing rates. As a result, a dishing effect occurs and reduces the resolution of lithography.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a dummy pattern, comprising the following steps. A semiconductor substrate having a dense region and a sparse region is provided. Conducting patterns are formed on the dense region. A dielectric layer is formed over the substrate and the conducting patterns. Photoresist patterns are formed on the dielectric layer above the rare region. The dielectric layer is etched back to form a plurality of spacers on the sidewalls of the conducting patterns, and, simultaneously, a plurality of dummy patterns is formed on the sparse region. The photoresist patterns are removed.
As embodied and broadly described herein, an inter-dielectric layer is further formed over the substrate to cover the conducting patterns and the dummy patterns after the dummy patterns are formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5639697 (1997-06-01), Weling et al.
patent: 5861342 (1999-01-01), Gabriel et al.
United Microelectronics Corp.
Wilson Christian D.
Zarabian Amir
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