Method of manufacturing contact structure

Details Method of manufacturing contact structure Method of manufacturing contact structure

2000-07-05

2002-01-08

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000, C438S701000

Reexamination Certificate

active

06337268

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for manufacturing a contact structure adopted in a multilayer interconnection structure.
2. Description of the Background Art
Conventionally, multilayer interconnection structures have adopted the so-called contact structure to establish electrical connections via an interlayer insulation film.
FIGS. 8
to
10
are cross-sectional views showing, in the sequence of operations, a conventional method of manufacturing a contact structure.
On a substrate
1
for example formed of a semiconductor or insulator, a plurality of wires
4
are selectively provided. The substrate
1
and the wires
4
are covered with an interlayer insulation film
2
consisting of first to third insulation films
21
to
23
which are stacked on top of each other in this order. The first insulation film
21
and the third insulation film
23
are, for example, p-TEOS (tetraethylorthosilicate) oxide films doped with phosphorus, which are formed by CVD with TEOS as source gas. The second insulation film
22
is for example an insulation film formed by SOG (Spin-On-Glass). The use of such a multilayer structure allows the interlayer insulation film
2
to have excellent step coverage and good surface planarity.
On the third insulation film
23
, a resist
3
is formed in such a pattern that portions of the third insulation film
23
above the wires
4
are exposed (FIG.
8
).
In the contact structure, isotropic etching using the resist
3
as a mask (e.g., wet etching) is performed for such a reason that a taper is formed thereabove, whereby upwardly widened openings
51
are formed in the third insulation film
23
as shown in FIG.
8
.
Then, the portions of the second insulation film
22
exposed to the openings
51
and further the corresponding portions of the first insulation film
21
are anisotropically etched in this order by dry etching, whereby openings
52
are formed in the first and second insulation films
21
and
22
. This results in the structure shown in
FIG. 10
in which the upper surfaces of the wires
4
are exposed to through holes
5
each consisting of the openings
51
and
52
which communicate with each other.
After the resist
3
is removed and the through holes
5
are filled with conductive materials, different wires are formed in contact with the conductive materials on the third insulation film
23
. This provides electrical connections between the additional wires and the wires
4
via the conductive materials with the interlayer insulation film
2
therebetween, resulting in the formation of a contact structure in the multilayer interconnection structure.
The process shown in
FIG. 9
(i.e., the process of forming the openings
51
in the third insulation film
23
by wet etching), however, has a problem that voids may be made between the first insulation film
21
and the third insulation film
23
since the second insulation film
22
once exposed can easily be etched.
To overcome this problem, Japanese Patent Laid-open No. P07-74172A, for example, has proposed a technique for etching back the whole surface after the formation of the second insulation film
22
on the first insulation film
21
and before the formation of the third insulation film
23
. This technique allows only the portions of the second insulation film
22
above the wires
4
to be removed while leaving the second insulation film
22
between the adjacent wires
4
. At this time, etch selectivity of both the second insulation film
22
and the wires
4
is set low; therefore, not only the second insulation film
22
but also the first insulation film
21
on the wires
4
are etched.
However, if the whole surface is etched back to the extent that the first insulation film
21
on the wires
4
is etched, the surface of the second insulation film
22
sandwitched between the adjacent wires
4
is likely to be below that of the first insulation film
21
on the wires
4
even if the etch selectivity is set low. This is undesirable in terms of surface planarity.
SUMMARY OF THE INVENTION
The present invention is directed to a method of manufacturing a contact structure, comprising the steps of: (a) selectively forming a plurality of wires on a substrate; (b) forming a first insulation film to cover the substrate and the wires, the first insulation film having an exposed surface on the opposite side to the substrate; (c) forming a second insulation film, which is coating glass, on the first insulation film; (d) etching back a structure obtained in the step (c) to expose portions of the surface above the wires; (e) forming a third insulation film on a structure obtained in the step (d); (f) forming, on the third insulation film, a mask having a pattern to expose portions of the third insulation film above the wires; (g) performing isotropic etching using the mask to form a first opening in the third insulation film, the first opening exposing a portion of the surface above each of the wires; (h) performing anisotropic etching through the first opening to form a second opening in the first insulation film, the second opening communicating with the first opening and exposing each of the wires; and (i) filling the first opening and the second opening with a conductive material and forming another wire in contact with the conductive material on the third insulation film.
According to the present invention, etching can be stopped with little removal of the first insulation film. This prevents the surface of the second insulation film sandwiched between the adjacent wires from being below that of the first insulation film on the wires, thereby ensuring good surface planarity. Further, the isotropic etching does not remove the second insulation film. This prevents the occurrence of voids in the interlayer insulation film consisting of the first to third insulation films, thereby allowing the formation of a contact structure that provides electrical connections between the wires and additional wires via the conductive material with the interlayer insulation film therebetween.
An object of the present invention is to provide a technique for obtaining a contact structure with no voids in the interlayer insulation film and good surface planarity.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5082801 (1992-01-01), Nagata
patent: 5502006 (1996-03-01), Kasagi
patent: 5672241 (1997-09-01), Tien et al.
patent: 5858882 (1999-01-01), Chang et al.
patent: 6143666 (2000-11-01), Lin et al.
patent: 196 08 883 (1997-01-01), None
patent: 0 523 856 (1992-06-01), None
patent: 3-149826 (1992-06-01), None
patent: 7-74172 (1995-03-01), None
patent: 7-704172 (1995-03-01), None
patent: 7-122635 (1995-05-01), None

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