Method of manufacturing CMOS transistor by using SOI substrate

Details Method of manufacturing CMOS transistor by using SOI substrate Method of manufacturing CMOS transistor by using SOI substrate

2007-08-07

2007-08-07

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S300000, C257SE21634

Reexamination Certificate

active

11020238

ABSTRACT:
In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.

REFERENCES:
patent: 5731217 (1998-03-01), Kadosh et al.
patent: 5818069 (1998-10-01), Kadosh et al.
patent: 6235567 (2001-05-01), Huang

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