Method of manufacturing CMOS semiconductor device

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor

Reexamination Certificate

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C438S162000, C257S069000

Reexamination Certificate

active

06881653

ABSTRACT:
A method of manufacturing a CMOS semiconductor device able to reduce the effective thickness of the gate insulating film and able to secure stable performance is provided. The method in one embodiment comprises the steps of: forming a polycrystalline silicon film on a gate insulating film; introducing an n-type impurity into the polycrystalline silicon film in an nMOS formation region before gate processing of the polycrystalline silicon film; performing heat treatment so that the impurity diffuses in the polycrystalline silicon film and is activated; and patterning the polycrystalline silicon to form a gate pattern before introducing an impurity into the polycrystalline silicon film at a pMOS formation region.

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patent: 6-310666 (1994-11-01), None
Sugatani et al., “Requirements for Dry Process of 100 nm, node CMOS Integration”, Dry Process International Symp. 2002, p255-262.
Wen-Chin et al.; Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si0.8Ge0.2Gate PMOS Devices; vol. 20., No. 1., Jan. 1999.

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