Method of manufacturing CMOS device

Details Method of manufacturing CMOS device Method of manufacturing CMOS device

1999-12-28

2001-07-10

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S723000

Reexamination Certificate

active

06258722

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a CMOS device capable of isolating a N well and a P well in back side of a substrate.
2. Description of the Related Art
A complementary metal oxide semiconductor(CMOS) device has a combination structure of a N-channel MOS(NMOS) transistor and a P-channel MOS(PMOS) transistor. This CMOS device has the advantage of a low power consumption compared with a single device such as a NMOS or a PMOS transistor, since DC voltage between power supply terminals is very low. Therefore, the CMOS device is appropriated for low power, high speed and high integration devices.
When manufacturing the CMOS device, for forming NMOS and PMOS transistors respectively, a N well and a P well are necessarily formed. Furthermore, the N well and the P well are isolated by PN junction.
However, in the above CMOS device, a parasitic thyristor exists due to PNPN junction. Therefore, in case voltage is extremely applied to an input terminal of the CMOS device due to noise of power supply voltage, the parasitic thyristor is turned-on. As a result, current extremely flows in the CMOS device, so that the CMOS device is broken. This occurrence is “latch-up”.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a CMOS device which can prevent latch-up and easily apply to high integration device by completely isolating a N well and a P well in the back side of a substrate, for solving the problems in the conventional art.
To accomplish this above object, a method of manufacturing a CMOS device according to the present invention, includes the steps of: providing a semiconductor having a back side and a front side, and including a N well and a P well formed therein respectively, a NMOS transistor formed on the P well, a PMOS transistor formed on the N well; etching the back side of the substrate along the PN junction portions of the N well and the P well to the front side of the substrate, thereby forming trenches; and forming an insulating layer on the back side of the substrate to fill the trenches, thereby isolating the P well and the N well.
Furthermore, a method of manufacturing a CMOS device according to the present invention, further includes the steps of: etching the insulating layer to expose the P well and the N well, thereby forming contact holes; forming a metal layer on the insulating layer to fill the contact holes; and patterning the metal layer to form an interconnection line.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4740827 (1988-04-01), Niitsu et al.
patent: 5179038 (1993-01-01), Kinney et al.
patent: 5489795 (1996-02-01), Yoshimura et al.
patent: 5612242 (1997-03-01), Hsu
patent: 5861330 (1999-01-01), Baker et al.
patent: 5877066 (1999-03-01), Stolmeijer et al.
patent: 6046079 (2000-04-01), Ko et al.
patent: 4263467 (1992-09-01), None

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