Method of manufacturing buried bit line DRAM cell

Details Method of manufacturing buried bit line DRAM cell Method of manufacturing buried bit line DRAM cell

1995-11-30

1998-11-24

Niebling, John

Fishing, trapping, and vermin destroying

437 47, 437 60, 437203, H01L 2170

Patent

active

058405917

ABSTRACT:
A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.

REFERENCES:
patent: 5618745 (1997-04-01), Kita
patent: 5627092 (1997-05-01), Alsmeier et al.
patent: 5629226 (1997-05-01), Ohtsuki

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