Method of manufacturing an overlay mark

Details Method of manufacturing an overlay mark Method of manufacturing an overlay mark

2008-04-29

2009-10-06

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S257000, C438S424000, C438S425000

Reexamination Certificate

active

07598155

ABSTRACT:
A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures.

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patent: 6798038 (2004-09-01), Sato et al.
patent: 7423312 (2008-09-01), Torii
patent: 2007/0194466 (2007-08-01), Yamaguchi

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