Method of manufacturing an interconnection structure

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S623000, C438S624000, C438S625000, C438S626000

Reexamination Certificate

active

07825023

ABSTRACT:
This invention relates to a process for manufacturing interconnection structures, including:a) the formation on a substrate of a first layer comprising one or several conducting zones (24) and one or several insulating zones made of an organic material (26),b) coverage of this first layer by a porous layer (28),c) consumption and elimination of at least part of the organic material through the porous layer, using enzymes and/or proteins.

REFERENCES:
patent: 5078802 (1992-01-01), Imanaka et al.
patent: 5750415 (1998-05-01), Gnade et al.
patent: 2002/0047207 (2002-04-01), Sekiguchi
patent: 2004/0137728 (2004-07-01), Gallagher et al.
patent: 2006/0014374 (2006-01-01), Barth et al.
patent: 2006/0040492 (2006-02-01), Goodner et al.
patent: 2641896 (1896-07-01), None
patent: 2239659 (1991-07-01), None
patent: 2004/001842 (2003-12-01), None
French Preliminary Examination Seach Report, FA 674554 and FR 0650443, 3 pgs, (Nov. 10, 2006).

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