Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1998-10-26
2001-04-17
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S397000
Reexamination Certificate
active
06218077
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to manufacturing an integrated circuit and, more particularly, to a method of manufacturing integrated circuits using scanning systems and methods.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) fabrication involves a process sequence in which patterns are generated in different material layers using, for example, a combination of deposition, lithography, and etching techniques. After the formation of a material layer on a silicon wafer, lithographic and etching techniques are used to transfer a desired pattern into the material, or to process the exposed substrate material. Typically, a radiation-sensitive material, called a resist, is spin-coated onto this material layer prior to lithographic printing. The lithographic printing step is usually performed using an imaging tool called a stepper, which has a high intensity light source, a relay lens, a reticle stage, an imaging lens and a high precision translation stage.
A reticle containing an IC pattern to be printed is illuminated by the high intensity light source, which may be a mercury arc lamp or a laser, at a specific wavelength that causes radiation-induced changes in the resist. The light passing through the reticle is imaged by the lens onto the resist layer on the wafer. After each exposure, the wafer is stepped by a translation stage to the next site for subsequent exposure. The wafer is positioned on the translation stage. This exposure step essentially generates a latent image of the circuit pattern in the resist, similar to the exposure of a photographic film in conventional photography. The exposed resist can then be developed to produce a patterned resist layer, which can be used as a mask in a subsequent processing step, which, for example, transfers this pattern onto the underlying material layer.
The pattern is formed using a thin layer of material opaque to the radiation. The opaque material may be a chrome layer formed on a quartz substrate. During the exposure step, illuminating light passes through the reticle at regions where chrome, the pattern material, is absent. The light that passes through the reticle travels through a lens to expose the resist on the substrate. The opaque material prevents light from passing through the reticle.
The resolution R of an optical system and the depth of focus DOF at its resolution limit are respectively expressed in equations (1) and (2) below.
R
=
k
1
⁢
λ
NA
(
1
)
DOF
=
k
2
⁢
λ
(
NA
)
2
(
2
)
&lgr; is the wavelength, NA is the numerical aperture of the projection optical system, and k
i
and k
2
are process dependent constants.
There is an increasing demand to shrink transistor size and increase circuit speed. One method of reducing transistor size is to enhance the resolution of the optical system by reducing the wavelength &lgr; and increasing the numerical aperture NA. Changing these parameters reduces the depth of focus DOF. For example, a typical deep ultraviolet (DUV) stepper having a wavelength &lgr; equal to 0.248 &mgr;m and a numerical aperture NA equal to 0.6 has a resolution R of approximately 0.3 &mgr;m and a depth of focus DOF of approximately 0.5 &mgr;m. This assumes k
1
=k
2
=0.8. Transferring the pattern from the reticle to the substrate becomes more difficult as the depth of focus decreases.
Efforts have been made to increase the effective depth of focus DOF. One such method is the focus latitude enhancement exposure process, also known as focus drilling. This method is described in A new method for enhancing focus latitude in optical lithography: Flex,
IEEE Electron Device Letters
, EDL-8, 179, (1987) by H. Fukuda et al.; and Using multiple focal planes to enhance depth of focus, SPIE 1674, Optical/Laser Microlithography V, 285, (1992) by C. A. Spence et al. Each of these documents are herein incorporated by reference.
During focus drilling, the same part of the wafer is exposed at different focal positions. This is achieved by moving the wafer stage in the Z direction while the stepper shutter is open. The image on the wafer is, therefore, an integration of multi-exposures at different focal positions. This method was developed for stepper tools having wafer stages, which did not perform X-, or Y-movement while the shutter is open. In other words, the wafer stage is in a fixed position in the X or Y-direction relative to the light source when the relative position of the substrate stage is changed in the Z direction.
Current lithography tools, however, are transitioning to scanner systems for critical level printing. In a scanner system, the reticle translation stage (the platform holding the reticle) and the substrate translation stage (the platform holding the substrate) are at constant motion when the shutter is open. As described above, the prior art technique uses a wafer stage that is maintained in a fixed position during exposure. Therefore, it would be difficult to implement the prior art focus drilling technique directly in a scanner system. Thus, it would be desirable to provide a system that improves the effective depth of focus DOF for present and future lithography technologies.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing an integrated circuit using an imaging system having a mask (a reticle) and an energy source that produces an exposure field. A substrate is moved across the exposure field while changing the depth of focus of the imaging system relative to the substrate. The depth of focus may be changed by moving the substrate, the mask, or both, relative to each other changes the depth of focus. The depth of focus may be oscillated according to a periodic waveform where the waveform is equal to the time for a typical point on the substrate to pass through the exposure field. It is to be understood that both the foregoing description and the following detailed description are exemplary, but are not restrictive, of the invention.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 04214612 (1992-08-01), None
patent: 4-214612 (1992-08-01), None
“A New Method For Enhaning Focus Latitude In Optical Lithography: FLEX”, H. Fukuda et al.,IEEE Electron Device Letters,vol. EDL-8, No. 4, Apr. 1987.
“Improvement Of Defocus Tolerance In A Half-Micron Optical Lithography By The Focus Latitude Enhancement Exposure Method: Stimulation And Experiment,” H. Fukuda et al., J. Vac. Sci. Technol., B7 (4), Jul./Aug. 1989.
Agere Systems Guardian Corp.
Duda Kathleen
Grillo Anthony
LandOfFree
Method of manufacturing an integrated circuit using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing an integrated circuit using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an integrated circuit using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2529928