Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-01
2003-09-30
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S549000
Reexamination Certificate
active
06627928
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to the manufacture of integrated circuits, and more particularly, to an electrically programmable, non-volatile memory and high-performance logic circuitry integrated in the same semiconductor chip.
BACKGROUND OF THE INVENTION
The development of integration techniques, which is directed towards the production of entire electronic systems or subsystems in a single semiconductor chip, involves the ability to integrate logic circuitry with memories having a high degree of complexity. In particular, there is an increasing need to integrate non-volatile memories, particularly of the electrically-programmable and erasable type, such as flash EEPROMs, in CMOS processes for the manufacture of high-performance logic circuitry, i.e., high-speed and low-consumption circuitry.
However, a combination of this type is becoming more and more difficult to achieve from a technological point of view because of the ever more different requirements, particularly in terms of operating voltages. In fact, on the one hand, the natural development of CMOS processes for high-performance logic circuitry leads to a progressive reduction in the operating voltage to enable the dimensions of the transistors to be reduced. The reduction in dimensions and in the operating voltage leads to a corresponding reduction in the thickness of the gate oxide and in the depth of the transistor junctions. On the other hand, electrically programmable, non-volatile memories require relatively high programming voltages, and in spite of the reduction in the dimensions of the memory cells, it is not considered possible to reduce these voltage values significantly in the near future, at least as far as floating-gate non-volatile memories are concerned.
With reference, for example, to 0.25 &mgr;m technology, the transistors produced by an advanced CMOS manufacturing process designed for high-performance logic circuitry are optimized for operating within a supply-voltage range from about 0.9 to 2.5 V. These transistors have gate oxides about 5 nm thick and source/drain junctions which can withstand a voltage no greater than about 8 to 10 V.
A flash EEPROM memory, on the other hand, requires a programming voltage within the range of 10 to 12 V for the programming of the memory cells. The programming voltage is even higher for other types of non-volatile memories. To be able to withstand these voltages, the transistors require gate oxides with a thickness within the range of 15 to 18 nm and source/drain junctions with breakdown voltages at least greater than the programming voltage.
It is not easy to reconcile these conflicting requirements. On the one hand, any attempt to modify the structure of the transistors within an advanced CMOS process to render them capable of withstanding the relatively high voltages required by non-volatile memories gives rise to an unacceptable reduction in the performance of the logic circuitry. On the other hand, complete duplication of the peripheral structures to produce both high-performance CMOS transistors and transistors which can withstand relatively high voltages greatly increases the number of photolithographic masks of the manufacturing process.
A method of manufacturing relatively high-density flash EEPROM memories, i.e., greater than 256 to 512 Kbits, requires two polysilicon levels. A lower level (the first poly) is used to form the floating gates of the memory cells, and an upper level (the second poly) is used to form both the control gates of the memory cells and the gates of the transistors of the memory service circuits, e.g., cell-selection, reading, and programming circuits. This method also requires at least two different gate oxide layers. One layer about 10 nm thick is formed between the surface of the substrate and the lower polysilicon level and acts as a gate oxide for the memory cells. The other layer, which is about 15 nm thick, is formed between the substrate and the upper polysilicon level and forms the gate oxide of the transistors of the service circuits.
In some methods of manufacture, to improve the performance of the memory at low supply voltages, transistors with a thin gate oxide layer (7 to 10 nm) are also provided. These transistors have gate electrodes formed from the second polysilicon level. However, in order to minimize the number of additional masks required, these transistors with thin gate oxides share many structural elements with the transistors with thicker gate oxides which control the relatively high voltages required, for example, for programming the memory cells.
When a non-volatile memory, for example, a flash EEPROM, is to be integrated by advanced CMOS manufacturing processes, the characteristics of the high-performance transistors must be preserved. In order to achieve this, the high-performance transistors cannot share structural elements with the transistors which control the relatively high voltages required by the memory cells. It is not enough to provide for the formation of two different gate oxide layers, and one or two additional masks for adjusting the threshold voltages. Additional masks would in fact be required to produce high-voltage junctions for the high-voltage transistors, and the number of additional masks could therefore easily become excessive.
SUMMARY OF THE INVENTION
In view of the prior art described above, an object of the present invention is to provide a readily manufactured integrated circuit including a non-volatile memory and high-performance logic circuit in the same semiconductor chip.
This and other objects, features and advantages in accordance with the present invention are provided by an integrated circuit comprising a semiconductor substrate, and a logic circuit on the semiconductor substrate. The logic circuit may comprise a plurality of first transistors on first portions of the semiconductor substrate operating at a first voltage, and each first transistor comprising a first gate oxide layer, a gate electrode on the first gate oxide layer, a first portion of a first dielectric layer covering the gate electrode, and a conducting layer covering the first dielectric layer. The logic circuit may also include a plurality of second transistors on second portions of the semiconductor substrate operating at a second voltage less than the first voltage, and each second transistor comprising a third gate oxide layer, and a gate electrode on the third gate oxide layer. The integrated circuit may also include a memory device on the semiconductor substrate. The memory circuit may comprise a plurality of memory cells on third portions of the semiconductor substrate, and each cell may comprise a second gate oxide layer, a floating gate on the second gate oxide layer, a second portion of the first dielectric layer on the floating gate, and a control gate on the second portion of the first dielectric layer.
The first gate oxide may have a first thickness, the second gate oxide has a second thickness, and the third gate oxide may have a third thickness less than the first thickness. For example, the first gate oxide layer may have a thickness in a range of about 100 to 300 angstroms, the second gate oxide layer may have a thickness in a range of about of about 70 to 110 angstroms, and the third gate oxide layer may have a thickness in a range of about 20 to 80 angstroms.
The memory device may comprise an EEPROM device, for example, and the logic device may comprise a CMOS logic device, for example. The plurality of first transistors may comprise at least one N-channel transistor and at least one P-channel transistor, and the plurality of second transistors may comprise at least one N-channel transistor and at least one P-channel transistor.
REFERENCES:
patent: 5622886 (1997-04-01), Allum et al.
patent: 5668034 (1997-09-01), Sery et al.
patent: 5768194 (1998-06-01), Matsubara et al.
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5908311 (1999-06-01), Chi et al.
patent: 5994757 (1999-11-01), Ichikawa et al.
patent: 6071775 (2000-06-01), Choi et al.
patent:
Maurelli Alfonso
Palumbo Elisabetta
Peschiaroli Daniela
Piazza Fausto
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nhu David
STMicroelectronics S.r.l.
LandOfFree
Method of manufacturing an integrated circuit, for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing an integrated circuit, for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an integrated circuit, for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3057733