Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1998-02-13
2000-05-16
Chang, Joni
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438455, 438928, 257350, H01L 2176, H01L 2130
Patent
active
060636866
ABSTRACT:
A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer. A gate insulating film for an MISFET is formed over the semiconductor layer; a gate electrode for the MISFET is formed over the gate insulating film, and source and drain region for the MISFET are formed in the semiconductor layer. With this arrangement, the first insulating film serves as a gate insulating film for the MISFET, and the semiconductor film serves as a gate electrode for the MISFET.
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Aoyama Kimiko
Ikeda Takahide
Masuda Hiroo
Mitani Shinichiro
Nakamura Takahide
Chang Joni
Coleman William David
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