Method of manufacturing an ESD protection device with the...

Details Method of manufacturing an ESD protection device with the... Method of manufacturing an ESD protection device with the...

Filed on

2006-05-23

Date issued

2006-05-23

Examiner

Wilson, Allan R. (Department: 2815)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257S336000, C257S408000

Type

Reexamination Certificate

Status

active

Patent number

07049659

Description

ABSTRACT:
A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

REFERENCES:
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patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5672527 (1997-09-01), Lee
patent: 5744372 (1998-04-01), Bulucea
patent: 5953601 (1999-09-01), Shiue et al.
patent: 6114226 (2000-09-01), Chang et al.
patent: 6396103 (2002-05-01), Riccobene et al.

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