Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-10-04
2005-10-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S618000, C438S710000, C438S725000, C438S761000, C438S780000, C438S781000
Reexamination Certificate
active
06951818
ABSTRACT:
A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).
REFERENCES:
patent: 6284149 (2001-09-01), Li et al.
patent: 6559070 (2003-05-01), Mandal
Blees Martin Hillebrand
Decre Michel Marcel Jose
Gelinck Gerwin Hermanus
Giesbers Jacobus Bernardus
Montree Andreas Hubertus
Berry Renee R.
Koninklijke Philips Electronics , N.V.
Zawilski Peter
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