Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-09-28
2002-04-16
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S610000, C438S640000, C438S692000, C438S738000, C438S580000
Reexamination Certificate
active
06372616
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an electrical interconnection on a semiconductor substrate using a damascene process.
2. Description of the Related Art
Copper (Cu), whose resistivity is about 40% lower than that of Al, is often used to form wiring including the electrical interconnections of semiconductor devices. First, the Cu is deposited on a substrate and then it is patterned to form the wiring. However, it is difficult to pattern a Cu layer by dry etching because of the low resistivity of the Cu. Accordingly, a damascene process has been developed, in which chemical mechanical polishing (CMP) is adopted, to form the wiring of a semiconductor device from a Cu layer.
The so-called single damascene process includes hole patterning steps for forming a conductive plug, and line patterning steps for forming a conductive line. Also, in the single damascene process, steps of depositing a wiring material layer, of forming a via contact hole or a recess, and of CMP are repeatedly carried out because the single damascene process is typically applied to manufacturing a semiconductor device having multiple interlayer dielectric layers. Still further, a capping layer of SiN is formed at the interfaces between the interlayer dielectric layers in order to prevent the wiring material such as Cu from diffusing to an interlayer dielectric layer.
Some steps of the process can be obviated by employing a so-called dual damascene process. However, the dual damascene process has a drawback in that a recess for the conductive line often produces a defect in a photoresist pattern required for the subsequent process of forming the via contact hole for the conductive plug.
More specifically, it is difficult to planarize the photoresist layer used for forming the contact hole, due to the depth of the recess. Accordingly, an alignment error typically occurs when exposing the photoresist. A rather thick photoresist layer may be used in an attempt to prevent such an error from occurring. In this case, however, the photoresist layer is not sufficiently exposed because of its thickness. Accordingly, an opening failure may occur in which the photoresist pattern does not expose the underlying layer at the bottom of the recess. For these reasons the dual damascene process makes it difficult to develop the photoresist layer correctly.
Also, like the single damascene process, dual damascene processes, such as a count-border dual damascene (CBDD) process or a self-align dual damascene (SADD) process, form an etch stopping layer of SiN at the interfaces between interlayer dielectric layers.
In any of the above-described damascene processes, the SiN remains over the entire interlayer dielectric layer. SiN has a relatively high dielectric constant k, namely one that is equal to or greater than 7. The effective dielectric constant of the entire interlayer dielectric layer becomes high due to the SiN. Accordingly, the semiconductor device may fail due to the high dielectric constant of the interlayer dielectric film. For example, a high dielectric constant of an interlayer dielectric film may cause a register-capacitor (RC) delay in a logic device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing an electrical interconnection of a semiconductor device using a dual damascene process by which it is possible to maintain a low dielectric constant of an interlayer dielectric layer.
To achieve the above object, the present invention provides a method of manufacturing an electrical interconnection in which a contact hole is formed in the interlayer dielectric layer, and the contact hole is filled with an erosion protecting plug of an organic material most of which remains in the contact hole until a recess for accommodating a conductive line is formed in the interlayer dielectric layer. The erosion protecting plug is formed of an organic material such as a photoresist material or an organic polymer. A photoresist pattern is formed which exposes both the erosion protecting plug and the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to and joins the contact hole is formed by etching the interlayer dielectric layer while the erosion protecting plug remains in the contact hole. The erosion protecting plug and the photoresist pattern are then removed. The recess and the contact hole are then filled with conductive material to form the conductive line.
According to the present invention, the electrical wiring is formed without the need for an etch stop layer or capping layer of a material layer such as SiN, which would otherwise effectively increase the dielectric constant of the interlayer dielectric layer.
REFERENCES:
patent: 6006764 (1999-12-01), Chu et al.
patent: 6022810 (2000-02-01), Kusumi et al.
patent: 6121149 (2000-09-01), Lukane et al.
patent: 6211071 (2001-04-01), Lukane et al.
Kim Il-gu
Lee Hyeon-deok
Yoo Bong-young
Lebentritt Michael S.
Luu Pho
Volentine & Francos, PLLC
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