Method of manufacturing an antifuse element having a controlled

Details Method of manufacturing an antifuse element having a controlled Method of manufacturing an antifuse element having a controlled

1997-02-26

1999-06-15

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438131, H01L 2900

Patent

active

059131381

ABSTRACT:
The present invention relates to the method of manufacturing an antifuse element having an antifuse layer formed between interconnection layers. Conventionally, an antifuse layer was formed after an aperture was formed through an interlayer insulating film. Such resulted in a thinner film thickness at the corner formed by inner wall surface of the aperture and a lower electrode layer. As it is very difficult to control the film thickness of the thinnest part to a specific value, control of the insulation breakdown voltage in "off" state was difficult. The present antifuse element includes a layer with a flat shape of an even thickness. The layer is a complexed film of amorphous silicon film, silicon nitride film and silicon oxide film. The antifuse electrode layer is of a titanium nitride, the film thickness of which is thicker than the invasion length of a fuse link into electrode layers. The step coverage of upper electrode layer is set to be higher than 80%, by controlling the film thickness of the insulation film separating the electrodes and the tapered shape of the aperture in the antifuse region.

REFERENCES:
patent: 5196724 (1993-03-01), Gordon et al.
patent: 5440167 (1995-08-01), Iranmanesh
patent: 5682058 (1997-10-01), Iranmanesh
patent: 5763299 (1998-06-01), McCollum et al.
patent: 5804500 (1998-09-01), Hawley et al.

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