Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-07-14
2001-02-20
Saadat, Mahshid (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S111000, C438S123000, C257S674000, C257S677000, C257S666000, C428S626000
Reexamination Certificate
active
06190939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the invention relates to a lead-on-chip (LOC) integrated circuit package which includes a multi-layered lead frame for improved heat dissipation and warp resistance.
2. Brief Description of the Related Technology
For greater heat dissipation, integrated circuit (IC) packages sometimes utilize a lead-on-chip (LOC) design, where a substantially planar lead frame is mounted to an IC die. The lead frame is usually comprised of a single electrically and thermally conductive material, such as copper or alloy
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. See U.S. Pat. Nos. 5,221,642 and 5,448,450, both assigned to the common assignee of the present invention. Other LOC IC packages include a single material lead frame which is electrically and thermally conductive and which is thinned in an area over the die to which it is mounted. See application Ser. No. 08/688,340, filed Jul. 30, 1996, assigned to the common assignee of the present invention.
To minimize the warping forces on an IC package, a warp resistant material having a coefficient of thermal expansion (CTE) selected to balance the warping forces extant on the IC package during assembly, testing or operation is mounted to one or more exterior surfaces of the IC package. Examples of such warp resistant packages and the techniques used to select the appropriate warp resistant material layers are described in U.S. Pat. Nos. 5,369,056, 5,369,058, and 5,581,121, and in application Ser. No. 08/644,491, filed May 10, 1996, pending, all assigned to the common assignee of the present invention.
A need exists for a LOC IC package which controls package warping, allows for improved thermal dissipation, but does not require a warp resistant material layer mounted to the package exterior or require that the LOC lead frame be thinned in an area directly over the die.
SUMMARY OF THE INVENTION
To resolve the need, the present invention includes an IC package in a LOC configuration which includes a multi-layered lead frame of uniform thickness over the active face of the die. The materials and thickness of the various layers of the lead frame are selected to ensure improved heat dissipation and to minimize package warping forces.
Preferably, the lead frame has three layers, with the first and third layers being copper, and the second layer being a warpage control material sandwiched between the first and third layers. The warpage control layer may be, for example, INVAR or alloy
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material which has the effect of lowering the CTE of the composite lead frame such that it approximates that of silicon. Using this type of LOC configuration, warp resistant material layers mounted to the package exterior are not necessary in many applications.
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Denko J. Scott
Diaz José R.
George & Donaldson, L.L.P.
Saadat Mahshid
Staktek Group L.P.
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