Method of manufacturing a wafer level package that uses the...

Details Method of manufacturing a wafer level package that uses the... Method of manufacturing a wafer level package that uses the...

2008-04-24

2010-06-01

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S615000, C438S674000, C257SE21586

Reexamination Certificate

active

07727877

ABSTRACT:
A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

REFERENCES:
patent: 7202156 (2007-04-01), Saiki et al.
patent: 2005/0040543 (2005-02-01), Watanabe
patent: 6-333931 (1994-12-01), None
patent: 2001-244287 (2001-09-01), None
patent: 2005-64473 (2005-03-01), None
Korean Office Action issued on Mar. 30, 2009 in corresponding Korean Patent Application 10-2007-0113931.

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