Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-08
2003-05-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S300000, C438S533000, C438S586000, C438S608000
Reexamination Certificate
active
06569721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor and more specifically, to a method of manufacturing a thin film transistor where the contact resistance between an impurity-doped silicon layer and an interconnecting metal line is reduced. The interconnecting metal line is in contact with the silicon layer and forms both the drain and pixel electrodes.
2. Description of the Background Art
Amorphous silicon (a-Si) TFT LCDs (Thin Film Transistor Liquid Crystal Displays) are increasingly being used in more diverse applications such as notebook PCs and desk top monitors. The growth of the TFT-LCD industry along with wider acceptance of TFT-LCD related applications have occurred because of the improvements in screen resolution and screen size of TFT LCDs. Further, the key to sustaining this growing trend is manufacturing TFT LCDs with greater productivity so that the price of TFT LCDs become more affordable to consumers. To realize significant gains in productivity, the manufacturing process must be simplified, and this can only occur if there is cooperation among all those involved in the manufacture of LCDs.
FIGS. 1A-1D
are cross-sectional views illustrating a process manufacturing a thin film transistor according to the prior art.
As shown in
FIG. 1A
, silicon oxide is deposited on an insulating substrate
100
such as glass to form a buffer oxide layer
102
. Polysilion is then deposited on the insulating substrate
100
and covers the buffer oxide layer
102
. The polysilicon is thereafter patterned via an etching process to form an active layer
104
.
Referring to
FIG. 1B
, a gate insulating layer
106
is formed on the buffer oxide layer
102
and covers the active layer
104
. The gate insulating layer
106
is formed by depositing silicon oxide via chemical vapor deposition (CVD). Next, a gate electrode
108
is formed so as to cover a selected portion of the active layer
104
. The gate electrode
108
is created by sputtering a metal such as aluminum or molybdenum to form a metal film, and then patterning the metal film via an etching process.
Thereafter, the entire surface of the insulating substrate
100
is heavily doped with n or p type impurity ions with the gate electrode
108
functioning as a mask. After the doping process, heavily doped impurity regions are formed within the active layer
104
on both sides of the gate electrode
108
. These regions serve as a source region S
1
and a drain region D
1
.
Referring to
FIG. 1C
, an interlevel insulating layer
110
covers the entire surface of the structure. It is then patterned via an etching process to create a first contact hole c
1
, which leaves the source region S
1
exposed. A source electrode
112
electrically connected to the source region S
1
is provided. Next, a protective layer
114
is deposited on the entire surface of the structure.
Referring to
FIG. 1D
, a second contact hole c
2
is created within the protective layer
114
and the interlevel insulating layer
110
, thus exposing the drain region D
1
. Thereafter, ITO (Indium Tin Oxide) is deposited on the protective layer
114
and then patterned via an etching process so as to cover the second contact hole c
2
. This process forms an interconnecting metal line
120
. The interconnecting metal line
120
serves both as a pixel electrode and a drain electrode because it is connected to the drain region D
1
of the active layer
104
.
Thus, in the prior art, the ITO is deposited directly on the drain region to form the interconnecting metal line. The direct contact between the drain region and the ITO causes an increase in the contact resistance between the drain region and the ITO because an oxide layer is formed therebetween. Therefore, a contact failure may occur in the interconnecting metal line when it is connected to the drain region.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a method for manufacturing a thin film transistor which greatly reduces contact resistance between an impurity-doped silicon layer and an interconnecting metal line without increasing the cost or difficulty of manufacturing the thin film transistor.
According to a preferred embodiment of the present invention, a method for manufacturing a thin film transistor includes providing an exposed drain region on an insulating substrate and covering the exposed drain region with a low resistance metal film.
According to another preferred embodiment, a method for manufacturing a thin film transistor includes forming an active layer on an insulating substrate, forming a gate insulating layer on the active layer, forming a metal film on the gate insulating layer, patterning the metal film to form a gate electrode, forming a source region and a drain region by heavily implanting a first conductivity type impurity into the active layer using the gate electrode as a mask, forming an interlevel insulating layer and exposing the source region by patterning the interlevel insulating layer, forming a source electrode on the source region, forming a protective layer and patterning the protective layer so as to expose the drain region on the interlevel insulating layer, covering the drain region with a low resistance metal film and forming an interconnecting metal line so as to cover the low resistance metal film.
According to another preferred embodiment of the present invention, a method of manufacturing a thin film transistor includes the steps of forming an active layer on an insulating substrate, applying a gate insulating layer on the active layer, sputtering a metal such as aluminum or molybdenum to form a metal film on the gate insulating layer, patterning the metal film to form a gate electrode, forming source and drain regions by heavily implanting impurity ions into the active layer using the gate electrode as a mask, forming an interlevel insulating layer covering the entire surface of the resulting structure and patterning the insulating layer so as to expose the source region, forming a source electrode covering the source region, forming a protective layer and patterning it to expose the drain region on the interlevel insulating layer, depositing a low resistance metal film so as to cover the drain region, and forming an interconnecting metal line that covers the low resistance metal film.
Another preferred embodiment provides a thin film transistor including an insulating substrate, a drain region on the insulating substrate and a low resistance metal film that covers the drain region.
Various other features, elements, and advantages of the present invention will be readily appreciated as the same becomes better understood with reference to the following detailed description of preferred embodiments when considered in connection with accompanying drawings.
REFERENCES:
patent: 5747379 (1998-05-01), Huang et al.
patent: 5840618 (1998-11-01), Kondo
patent: 5847410 (1998-12-01), Nakajima
patent: 6271122 (2001-08-01), Wieczorek et al.
patent: 6303422 (2001-10-01), Abe et al.
patent: 08-186264 (1996-07-01), None
patent: 09-203911 (1997-08-01), None
Kim Dong-Hwan
Park Won-Kyu
Fourson George
García Joannie Adelle
LG. Philips LCD Co. Ltd.
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