Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-06-25
2001-01-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S698000
Reexamination Certificate
active
06180510
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of providing a semiconductor device with a substantially planarized device surface through a polishing operation.
Generally, a semiconductor device is made of a silicon substrate and comprises a semiconductor substrate portion having a substrate surface. It is assumed that the semiconductor device further comprises a plurality of protruding portions protruding from the substrate surface. The protruding portions may be an Al wiring pattern.
The semiconductor device has a device surface in question and may comprise an integrated circuit formed under the device surface. The integrated circuit includes a large number of microelements known in the art.
The integrated circuit can be formed by use of a dry etching technique in which a resist pattern is formed on the device surface in the manner known in a art. To form the resist pattern on the device surface, a photo exposure device is often used.
In the manner which will presently be described, the photo exposure device comprises a light source and an optical system. The light source is for emitting an exposure light beam having a wavelength &lgr;. The exposure light beam is incident on the device surface to have a focus margin M. The optical system has a numerical aperture NA. In the dry etching technique, the resist pattern has a practical resolution R. The practical resolution R and the focus margin M are represented by:
R=k·&lgr;/NA
(1)
and
M=k′·&lgr;
/(
NA
) (2)
Herein, k and k′ represent given constants between 0.5 and 1, both inclusive.
In a case where the resist pattern is made to have an extremely small part in size, the practical resolution R must have a small value. To this end, it is necessary to shorten the wavelength &lgr; and to increase the numerical aperture NA, as will be understood from Equation (1). With the increase of the numerical aperture NA, the focus margin M is drastically reduced, as is obvious from Equation (2). In this connection, it is required to make the device surface be substantially planarized.
In order to planarize the device surface, use has widely been made of a method of reflowing a BPSG (boron-doped phospho silicate glass) film as disclosed by Karn et al in Solid State Technology, June 1985, pp. 171-179. Alternatively, an etchback method is well known and disclosed, for example, in Nikkei Microdevice, June 1988, pp. 33-46. In these methods, it is possible to locally planarize the device surface, specifically, to exclusively planarize the protruded portions that are closely adjacent to one another. However, it is impossible to effectively remove a step portion which will be produced between presence and absence of each of the protruding portions and between presence and absence of a group of the protruding portions that are closely adjacent to one another.
In order to substantially planarize the device surface, attention has been recently directed to a polishing technique or operation known in the art. For example, a method of planarizing the device surface through the polishing operation is disclosed by R. R. Uttecht et al in Proc. 1991 VMIC Conference, pp. 20-26. The method will hereunder be called a first conventional method. In the manner which will later be discussed with reference to the drawings, the first conventional method not only has a lower efficiency but also suffers a technical difficulty.
Another method is disclosed in Japanese Patent Prepublication No. 295239/1991 and will hereunder be called a second conventional method. In the second conventional method, it is impossible to effectively remove the above-mentioned step portion in the manner which will later be discussed with reference to the drawings.
The present inventor developed a method which is described in Japanese Patent Application No. 94677/1992 which is not yet available to the public. The method will hereunder be called a third conventional method. According to the third conventional method, the polishing operation for planarization can be achieved with both high efficiency and high precision.
However, the third conventional method increases the number of the process steps inevitably raising the manufacturing cost. When the polishing operation is redundantly continued, the device surface is excessively polished or overpolished in the manner which will later be discussed with reference to the drawing.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method of giving to a semiconductor device with a device surface which is substantially planarized through a polishing operation with a reduced number of processes and which avoids occurrence of overpolishing thereof.
Other objects of this invention will become clear as the description proceeds.
According to this invention, there is provided a method of providing a semiconductor device with a substantially planarized device surface through a polishing operation. The semiconductor device comprises a semiconductor substrate portion having a substrate surface and a protruding portion protruding from the substrate surface. The method comprises the steps of coating the substrate surface and the protruding portion with a first anti-polishing film, depositing an insulator film on the first anti-polishing film, the insulator film having a first polishing rate for the polishing operation, coating the insulator film with a second anti-polishing film having a polishing rate lower than the first polishing rate for the polishing operation, and applying the polishing operation to the second anti-polishing film and to the insulator film to produce the device surface that is substantially planarized.
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Stanley Wolf, Ph.D., “Silicon Processing For The VLSI Era,”Bipolar and BICMOS Process Integration, vol. 2: Process Integration, Lattice Press (1990), cover page and pp. 486-491.
W. Kern et al., “Borophosphosilicate Glasses For Integrated Circuits,”Solid State Technology, Jun. 1985, pp. 171-179.
Japanese Article published inNikkei Microdevices, Jun. 1988, pp. 33-46.
R.R. Uttecht et al., “A Four-Level-Metal Fully Planarized Interconnect Technology For Dense High Performance Logic and SRAM Applications,” VMIC Confernece, Jun. 11-12, 1991, pp. 20-26.
Bowers Charles
Burns Doane , Swecker, Mathis LLP
Kielin Erik J
NEC Corporation
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