Method of manufacturing a structure for reducing leakage...

Details Method of manufacturing a structure for reducing leakage... Method of manufacturing a structure for reducing leakage...

2001-05-22

2002-07-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S199000, C257S291000

Reexamination Certificate

active

06417074

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to methods for providing isolation between adjacent regions of an integrated circuit and more particularly to methods of reducing current leakage from an active region to a field oxide region in a circuit, such as an image sensor circuit.
BACKGROUND ART
Complementary metal-oxide-semiconductor (CMOS) technology is used in the design and fabrication of integrated circuits for many types of applications. CMOS technology uses n-type transistors (NMOS) and p-type transistors (PMOS) that are formed by doping selected regions of a substrate and by forming layers on the substrate. A p-type material, such as boron, may be introduced to a bulk silicon substrate in a blanket ion implantation step. Field oxide regions and n-type regions may then be formed using well known integrated circuit fabrication techniques. Similarly, the processes for depositing conductive and dielectric layers on the substrate to complete the circuit are known.
One general area for applying CMOS technology that has received significant attention is image capture and processing. Imaging applications include video, still photography, and navigation that is based upon optical detection. Linear or two-dimensional arrays of pixels are formed along the surface of the substrate, with each pixel periodically generating a signal having a current or voltage level that is indicative of the intensity of light incident to that pixel. A typical three-transistor pixel
10
that is used in current CMOS image sensors is shown in FIG.
1
. Sensors that use this technology are often referred to as CMOS active pixel sensors (APS). A timing diagram for the operation of the three-transistor pixel
10
is shown in FIG.
2
. In typical operation, a node N
1
is set to a predetermined voltage V
dd′
(which may be different than the circuit operating voltage V
dd
) by turning on an n-channel reset transistor
12
. The state of the reset transistor is determined by controlling a reset voltage (V
reset
). In
FIG. 2
, V
reset
goes high at time T
0
, causing the node N
1
to ramp to V
dd′
. At time T
1
, the reset transistor
12
is turned off and photoelectrons are generated by the incident light on a photodiode
14
. The photoelectrons are injected into node N
1
, reducing the voltage on that node by a value of V
sense
=V
dd′
−(I
photo
×T
illuminate
/C
N1
). In this equation, I
photo
is the photocurrent induced by the incident light, T
illuminate
is the illumination time period and C
N1
is the capacitance on node N
1
. Both V
dd′
and V
sense
can in principle be read out of the pixel through a source-follower
16
by activating a row-select transistor
18
. In a two-dimensional array of pixels, there typically are row-select transistors and column-select transistors that allow the pixels to be sequentially sampled. The row-select transistor
18
is activated by manipulating a row-select (RS) signal. The illumination on the pixel is then proportional to V
dd′
−V
sense
=I
photo
×T
illuminate
/C
N1
. Persons skilled in the art refer to this operation as Correlated Double Sampling (CDS). Sampling occurs at time T
2
before T
illuminate
and time T
3
during T
illuminate
. The pixel is reset at time T
4
, since V
reset
is caused to go high.
One of the major problems of using CMOS technology in imaging sensors is the relatively large dark current intrinsic to the CMOS process. A significant cause of the large dark current is the reverse-bias diode leakage in the photodiode
14
of a pixel, as well as in the source diffusion of the MOS field effect transistor (MOSFET)
12
connected to the photodiode. The diode leakage is often dominated by the edge leakage currents. Furthermore, in deep-submicron generations of CMOS technology, this leakage current will only increase and take major engineering efforts to suppress.
The physical layout of the CMOS APS pixel
10
of
FIG. 1
will be described with reference to
FIGS. 3
,
4
and
5
.
FIG. 3
is a top view of the circuit layout of the APS pixel of
FIG. 1
, showing the various layers and diffusion regions.
FIG. 4
is a top view that isolates the active area diode of
FIG. 3
, while
FIG. 5
is a side sectional view of FIG.
4
. The active area diode is illustrated as being an n+/p diode fabricated in a p-substrate or p-well. However, the descriptions of the operations and problems apply equally to a p+
diode in an n-substrate or n-well. The pn-junction of the diode
14
is defined by the p-substrate or p-well
20
, which will be referred to as the p-layer. Electrical connections
22
and
24
to the diode are formed by depositing layers that are in contact with an n+ region
26
and a p+ region
28
, respectively. The n+ region
26
may be formed by ion implantation or other doping techniques into the active area that is identified as the photodiode
14
in FIG.
3
. The active area is delineated by a field oxide (FOX) region
30
. Typically, the FOX region is a thick layer of silicon dioxide (SiO
2
) that electrically isolates the active area from other regions of the substrate, which is typically a silicon substrate. There are several well known processes for forming the FOX. Any of the processes may be used to form the FOX of
FIGS. 3-5
. However, each of the known processes is susceptible to the formation of a high density of defects at the edges of the FOX. The defects are primarily due to mechanical stress effects and contamination. The high density of defects located within the pn-junction diode's depletion region contributes to the high reverse-bias leakage current found at the field-edge of the diode. There has been much research and development regarding providing process steps (such as oxide deposition, etching and annealing) that minimize the edge leakage. However, the edge leakage problem is expected to become worse as the CMOS process is applied at the deep-submicron level.
Referring specifically to
FIGS. 1 and 3
, the gates of the three transistors
12
,
16
and
18
are formed by a patterned polysilicon layer. The polysilicon layer is identified by hatching in FIG.
3
. The reset transistor
12
has a gate
32
, the row-select transistor
18
has a gate
34
, while the transistor
16
has a gate
36
that is electrically coupled to the N
1
node
22
. The source/drain regions of the three transistors are formed by diffusions using the appropriate dopants. As can be seen in
FIGS. 1 and 3
, the transistors
16
and
18
have source/drain regions that are formed by a common diffusion region
38
.
Dark current in the CMOS APS pixel
10
with an active area photodiode
14
is caused mainly by the photodiode leakage, which bleeds charge from the node
22
(N
1
). This reduces the voltage on the node, even when the reset transistor
12
is turned off during the illumination time T
illuminate
. Therefore, the diode leakage produces an offset in the differential voltage produced by the illumination, given by V
dd′
−(I
photo
+I
dark
)×T
illuminate
/C
N1
. For low light illumination, it is possible for I
dark
to be approximately the same as I
photo
. Thus, the dark current limits the dynamic range of the image sensor. Dark current reduction has usually been addressed by attempting to lower the intrinsic diode leakage of the CMOS technology via processing steps. This minimization of the diode leakage characteristics is very difficult in advanced deep-submicron CMOS technologies that use advanced field oxide formation techniques and have much higher doping concentrations in the diode.
Field-edge leakage can also be a significant problem at the transistor level of the pixel
10
. Each of the three MOSFETs
12
,
16
and
18
is formed by growing a thin gate oxide over the active area of the transistor and then forming the gates
32
,
34
and
36
by patterning strips of polysilicon over the thin gate oxide. The n+ dopant is implanted after the gates have been formed. For each transistor, two separate n+/p

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