Method of manufacturing a semiconductor memory device

Details Method of manufacturing a semiconductor memory device Method of manufacturing a semiconductor memory device

1999-04-12

2003-04-22

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Gettering of semiconductor substrate

C438S243000, C438S058000, C438S402000, C438S310000, C438S471000

Reexamination Certificate

active

06551866

ABSTRACT:

BACKGROUND OF THE INVENTION
FILED OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor memory device, in particular a method of gettering a silicon on insulator (hereinbelow referred to as SOI) element.
DISCUSSION OF BACKGROUND
In recent years, an SOI element formed by arranging an element on a single crystalline silicon formed on an insulator is utilized for promoting a high speed and microminiaturization. Further, it is proposed that a dynamic random access memory (DRAM) is fabricated in combination with a capacitor.
FIGS. 14
a
,
14
b
,
15
a
, and
15
b
show steps of a method of manufacturing a DRAM cell as an example of a conventional semiconductor memory device utilizing such an SOI element. At first, as shown in
FIG. 14
a
, an SOI substrate obtained by forming an SOI layer
103
made of single crystalline silicon on an insulator
102
arranged on a silicon substrate
101
is prepared and an inter-element isolation
104
made of silicon oxide or the like is formed in a side of the SOI layer
103
on the insulator
102
.
In the next, a MOSFET is formed as shown in FIG.
14
b
, wherein source drain areas
103
a
and
103
b
are formed in the SOI layer
103
by injecting impurities; a gate oxide film
108
a
is formed on a part of the SOI layer
103
between the source drain areas; and a gate electrode
108
is formed on the gate oxide film
108
a.
In the next, as shown in
FIG. 15
a
, a trench
105
is formed after forming the above MOSFET in order to fabricate a capacitance in the vicinity of MOSFET; and polycrystalline silicon (hereinbelow, referred to as polysilicon)
107
to be a storage node is formed by depositing polysilicon and patterning it after forming a silicon oxide film
106
by oxidizing an inner wall of the trench
105
, whereby a capacitor fabricated by the silicon substrate
101
, the silicon oxide film
106
in the trench, and a storage node
107
formed on the silicon oxide film
106
in the trench is obtained.
The polysilicon
107
is formed to extend from an opening portion of the trench
105
and is connected to the source drain area
103
b
of the SOI layer
103
on the source drain area
103
b
. In this, the polysilicon
107
to be the storage node is injected with conductive impurities so that the polysilicon becomes conductive.
As described, the DRAM cell is fabricated by forming the insulating layer
109
on the SOI substrate, forming a contact hole
110
in which a conductor is embedded on the source drain area
103
a
of the SOI layer and connecting the conductor in the contact hole
110
to an aluminum (Al) bit line
111
formed on the insulating layer
109
after forming the MOSFET and the storage node of the capacitor.
Generally, in a case that a MOSFET is formed in single crystalline silicon for making an SOI element, heavy metal atoms such as Fe, Cr, and Ni are mixed to single crystalline silicon and thereby the single crystalline silicon is contaminated by the heavy metal atoms in a step of producing a SOI substrate or a step of forming a source, a drain, or the like before forming a gate oxide film. However, because an insulator existed under the single crystalline silicon in such an SOI element, the heavy metal atoms could not diffuse toward a gettering site of the silicon substrate positioned under the insulator through the insulator, wherein effective gettering was not obtainable.
Accordingly, in the method of manufacturing the semiconductor memory device shown in
FIGS. 14
a
through
15
b
, heavy metal atoms were contained in single crystalline silicon during steps of producing it and therefore the heavy metal atoms contained in the SOI layer
103
of the single crystalline silicon were taken in a gate oxide film
108
a
when the gate oxide film
108
a
is formed to thereby cause leaks in the gate oxide film and failures in dielectric breakdown characteristics, and/or were taken in defects existing in a junction between source drain areas
103
a
,
103
b
and a channel area to thereby drop a yield.
It is proposed in, for example, JP-A-10-209167 (hereinbelow referred to as conventional technique
1
) and JP-A-6-132292 (hereinbelow referred to as conventional technique
2
) as a method of performing gettering that polycrystalline silicon for gettering is newly provided in an SOI layer or on the SOI layer in a semiconductor memory device formed with MOSFET using an SOI element.
In the conventional technique
1
, contaminants contained in single crystalline silicon were gettered by a region of polycrystalline silicon by selectively forming the region of polycrystalline silicon for gettering in the single crystalline silicon before forming a gate oxide film.
Further, in the conventional technique
2
, contaminants contained in single crystalline silicon was gettered by a polycrystalline silicon film by forming the polycrystalline silicon film for gettering on the single crystalline silicon before forming a gate oxide film. By applying the conventional technique
1
or
2
to the method of manufacturing a semiconductor memory device shown in
FIGS. 14
a
through
15
b
, it becomes possible to conduct gettering with respect to a DRAM cell utilizing the above SOI element.
However, there were problems that the number of steps of a manufacturing process was increased because it was necessary to newly form polycrystalline silicon for gettering and microminiaturization of an element became difficult because the width of the element and/or the thickness of the element was increased by newly providing a region for gettering in single crystalline silicon and newly forming a film for gettering on the single crystalline silicon.
On the other hand, when the width of the element and/or the thickness of the element was reduced in order to microminiaturize the element, in the conventional technique
1
, a region in which a polycrystalline silicon region was formed became narrow as a result of reduction of the width of the element; and in the conventional technique
2
, the thickness of the polycrystalline silicon film to be formed became thin as a result of reduction of the thickness of the element, whereby there was a problem that sufficient gettering could not be conducted. Thus, similar problems still remained even though the conventional technique
1
or
2
was applied to the method of manufacturing the semiconductor memory device shown in
FIGS. 14
a
through
15
b.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above-mentioned problems inherent in the conventional techniques and to provide a method of manufacturing a semiconductor memory device in which a sufficient gettering effect is obtainable even though the width of an element and/or the thickness thereof is reduced along with microminiaturization of the element.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, in which a MOSFET in single crystalline silicon formed on an insulator and a capacitor including a storage node positioned in the vicinity of the single crystalline silicon are provided, comprising: a step of forming the storage node by forming a conductive layer to be the storage node in the vicinity of the single crystalline silicon formed on the insulator and connecting the conductive layer to the single crystalline silicon, a step of gettering in which the single crystalline silicon is subjected to heat treatment after the step of forming storage node and contaminants contained in the single crystalline silicon are gettered by the conductive layer connected to the single crystalline silicon, and a step of forming a gate oxide film on the single crystalline silicon after the gettering step.
According to a second aspect of the present invention, the above-mentioned capacitor may be a stack-type capacitor having the conductive layer to be the storage node formed on the single crystalline silicon and an upper electrode formed on the conductive layer so as to be opposite to the conductive layer or a trench-type capacitor in which t

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