Method of manufacturing a semiconductor memory device

Details Method of manufacturing a semiconductor memory device Method of manufacturing a semiconductor memory device

1999-10-28

2002-01-15

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S239000, C438S253000, C438S737000

Reexamination Certificate

active

06339008

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. Hei 10(1998)-309290 filed on Oct. 30, 1998, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor memory device having a capacitor structure in which a ferroelectric film is disposed as a capacitance insulating film.
2. Description of the Related Art
In recent years, ferroelectric non-volatile memories (FeRAM) having high density and operating at high speed have been developed vigorously. As a background therefor, it can be mentioned that the amount of accumulated charges decreases with refinement of memory cells. Therefore, ferroelectric films having much higher dielectric constant than that of silicon oxide films or silicon nitride films used so far have become in use as the capacitance insulating films.
Further, for making three dimensional structures, a stack structure has been proposed in which a plug comprising polysilicon or tungsten is formed on the source of MOSEFT and capacitor is formed thereon.
A method of forming such a conventional non-volatile memory having the stack structure, particularly, a capacitor with a ferroelectric film, is to be explained below with reference to FIG.
2
.
At first, a semiconductor element having a diffusion region
12
is formed on the surface of a semiconductor substrate
17
. Subsequently, an interlayer insulating film
11
is formed on the semiconductor element and flattened. Thereafter, a contact hole is opened on the diffusion region
12
, where a contact plug
13
is formed (FIG.
2
(
a
)).
Subsequently, films of a lower barrier metal material
15
a
, a lower electrode material
14
a
, a ferroelectric material
18
a
and an upper barrier metal (not illustrated) are successively formed, on which a film of an upper electrode material
19
a
is formed (FIG.
2
(
b
)).
After forming all this series of films, if the different films in three layers made of the upper electrode material
19
a
(including upper barrier metal), the ferroelectric material
18
a
and the lower electrode material
14
a
(including lower barrier metal) can be etched continuously by using an identical mask, there is no need for taking misalignment of the layers into consideration. For this purpose, it is required for the etching conditions applicable in common with the three layers to provide a high selective ratio with respect to the masking material.
However, since a vapor pressure of reaction products formed by reaction with an etching gas in dry etching is extremely low, etching proceeds in each of the electrode materials only under an etching condition with an importance being attached to a physical sputtering effect mainly by ion impact. Accordingly, it has been extremely difficult to obtain an etching condition having a high selective ratio between the mask materials and the underlying materials and, accordingly, it has been difficult to pattern the series of films by an identical mask material.
For this reason, in the existent method, patterning has to be conducted while re-preparing masks on every layer, as shown in FIG.
2
(
c
) to FIG.
2
(
e
), in such a manner that an upper electrode
19
is formed with a first mask (FIG.
2
(
c
)), then a ferroelectric film
18
is formed with a second mask (FIG.
2
(
d
)) and, further, a lower electrode
14
is formed with a third mask (FIG.
2
(
e
)). Patterning is conducted so that a pattern of an upper layer does not extend beyond a pattern of a lower layer in consideration of potential misalignment between the layers.
Further, in Japanese Patent Laid-Open No. 135007/1997, a method other than that described above has been proposed. The method of manufacturing a semiconductor device described in this publication is to be explained below as another existent example.
In this existent example, after forming a lower electrode by pattering, a first insulating film is formed thereon and then it is flattened by etching back. Then, a second insulating film is deposited, a hole is disposed to the second insulating film at a position corresponding to the lower electrode, a ferroelectric film is formed over the entire surface on the second insulating film including the hole and then only the ferroelectric film on the second insulating film is removed selectively by a chemical-mechanical polishing (CMP) method, thereby to bury the ferroelectric film and, successively, an upper electrode is formed.
As a result, fine patterning of the ferroelectric film is enabled without using dry etching.
However, in the existent example shown in
FIG. 2
, while the problem involved in the dry etching patterning described above can be avoided by re-preparation of masks on every layer, the mask size has to be determined considering an alignment margin on every layer. As a result, the size is made smaller in the order of the lower electrode
14
, the ferroelectric film
18
and the upper electrode
19
, so that the cell size of the capacitor is enlarged compared with a case of applying pattering by using an identical mask. That gives rise to a problem from the viewpoint of refinement.
Further, the second existent example shows the method of depositing the first insulating film on the lower electrode, then flattening the first insulating film, further depositing the second insulating film, then disposing the hole to the second insulating film at the position corresponding to the lower electrode and burying the ferroelectric film. That is, the ferroelectric film is formed on the underlying layer having an evenness on the lower electrode formed by removing the first and the second insulating films. Further, an unetched portion is liable to be caused due to a step formed between the surface of the second insulating film and the surface of the lower electrode. Accordingly, it is difficult to obtain stable film characteristics for the ferroelectric film.
In addition, there is also another problem that no convenient slurry (polishing chemical liquid) suitable to ferroelectric material to be used in the succeeding CMP step has yet been developed.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a semiconductor memory element, which comprises:
a step of laminating and flattening a first interlayer insulating film on a semiconductor substrate provided with a semiconductor device having a diffusion region and then forming a contact hole in the first interlayer insulating film on the semiconductor element,
a step of forming a contact plug by burying a contact plug material into the contact hole,
a step of laminating a first electrode material forming a lower electrode for a capacitor so as to cover at least the contact plug and forming a lower electrode on the contact plug by patterning using a first mask,
a step of forming a second interlayer insulating film so as to cover the lower electrode, and flattening the second interlayer insulating film until the surface of the second interlayer insulating film reaches a height identical with the surface of the lower electrode,
a step of forming a ferroelectric material film and a second electrode material film forming an upper electrode for the capacitor in this order at least on the surface of the lower electrode,
a step of forming an upper electrode by patterning the second electrode material using a second mask and
a step of forming a ferroelectric film by patterning the ferroelectric material film using a third mask.
An example of a method of manufacturing a semiconductor memory device according to the present invention is to be explained with reference to FIG.
1
(
a
) to FIG.
1
(
e
), but the constitution of the invention is not restricted to the figures.
In
FIG. 1
, are shown a first interlayer insulating film
1
, a diffusion region
2
of a semiconductor device, a contact plug
3
, a lower electrode
4
, a barrier metal
5
of the lower electrode
4
, a second interlayer insulating film

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