Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1993-06-01

1994-08-30

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 156657, 1566611, 156662, 437 41, 437 67, H01L 21306, B44C 122

Patent

active

053424808

ABSTRACT:
An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a semiconductor substrate or a semiconductor layer, each groove extending into the substrate or layer and forming island regions of the substrate or layer, forming a burying material and a first mask having an etching rate greater than that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of the island regions and in the grooves, such that the film thickness is made virtually uniform for each of the surfaces, forming a second mask on the surface of the first mask, through which the region on each of the island regions is exposed and in which the end of the opening is situated from the end of the island region to the outside of the island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and applying isotropic etching successively to each of the first mask and the burying material by using the second mask as an etching mask, under a condition in which the etching rate for the first mask is greater than that for the burying material.

REFERENCES:
patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4657630 (1987-04-01), Agatsuma
patent: 4892614 (1990-06-01), Chapman et al.
patent: 5256592 (1993-10-01), Matsushita
Kurosawa et al., A new Bird's-Beak Free Field Isolation Technology for VLSI Devices, IEDM, 1981, pp. 384-387.

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