Method of manufacturing a semiconductor integrated circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S369000

Reexamination Certificate

active

07075157

ABSTRACT:
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased. Side wall spacers can be provided on the sides of the gate electrodes of the MISFETs and on the sides of the local wiring lines, and connection holes to semiconductor regions of these MISFETs are self-aligned to both the gate electrodes and the local wiring lines, whereby capacitor area can be increased and integration of the device can also be increased.

REFERENCES:
patent: 4549340 (1985-10-01), Nagasawa et al.
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4882289 (1989-11-01), Moriuchi
patent: 5079611 (1992-01-01), Ikeda et al.
patent: 5114879 (1992-05-01), Madan
patent: 5135882 (1992-08-01), Karniewicz
patent: 5145799 (1992-09-01), Rodder
patent: 5239196 (1993-08-01), Ikeda et al.
patent: 5296729 (1994-03-01), Yamanaka et al.
patent: 5298782 (1994-03-01), Sundaresan
patent: 5523598 (1996-06-01), Watanabe et al.
patent: 5554554 (1996-09-01), Bastani et al.
patent: 5610856 (1997-03-01), Yoshizumi et al.
patent: 5661325 (1997-08-01), Hayashi et al.
patent: 5700704 (1997-12-01), Ikeda et al.
patent: 5700705 (1997-12-01), Meguro et al.
patent: 5731219 (1998-03-01), Ikeda et al.
patent: 5754467 (1998-05-01), Ikeda et al.
patent: 5780910 (1998-07-01), Hashimoto et al.
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 5986309 (1999-11-01), Fujimoto et al.
patent: 61-66296 (1986-04-01), None
patent: 4-279056 (1992-10-01), None
patent: 04279056 (1992-10-01), None
Balasubramanian, et al., “Monolithic Storage Cell Having Inherent Latent Image Memory Operation”, IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3634-3635.
Japanese Office Action (Notification of Reason for Refusal), for Application No. JP- Hei 8(1996)-035872, dated Aug. 9, 2005.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing a semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor integrated circuit... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3550133

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.