Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-07-12
2011-07-12
Wagner, Jenny L. (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE23174
Reexamination Certificate
active
07977238
ABSTRACT:
A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
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E. T. Ogawa et al, “Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads,” Texas Instruments Inc., IEEE 02CH37320, 40thAnnual International Reliability Physics Symposium, Dallas, 2002. pp. 312-321.
Aoki Hideo
Funakoshi Takako
Murakami Eiichi
Okuyama Kousuke
Oshima Takayuki
Antonelli, Terry Stout & Kraus, LLP.
Renesas Electronics Corporation
Wagner Jenny L.
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