Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2007-02-13
2008-12-02
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S752000, C257SE21124
Reexamination Certificate
active
07459374
ABSTRACT:
A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
REFERENCES:
patent: 5442205 (1995-08-01), Brasen et al.
patent: 7202124 (2007-04-01), Fitzgerald et al.
patent: 7256142 (2007-08-01), Fitzgerald
patent: 2002/0072130 (2002-06-01), Cheng et al.
patent: 2003/0203600 (2003-10-01), Chu et al.
patent: 2003/0215990 (2003-11-01), Fitzgerald et al.
patent: 2004/0075105 (2004-04-01), Leitz et al.
patent: 2004/0178406 (2004-09-01), Chu
patent: 2005/0179028 (2005-08-01), Chen et al.
patent: 2006/0151787 (2006-07-01), Chen et al.
patent: 1 439 570 (2004-07-01), None
patent: 1 447 839 (2004-08-01), None
patent: WO 02/33746 (2002-04-01), None
M. L. Lee, Minjoo et al., “Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors”, Journal of Applied Physics, vol. 97, 011101 (2005).
Aulnette Cécile
Daval Nicolas
Figuet Christophe
Geyer Scott B.
Nikmanesh Seahvosh J
S.O.I.Tec Silicon on Insulator Technologies
Winston & Strawn LLP
LandOfFree
Method of manufacturing a semiconductor heterostructure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor heterostructure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor heterostructure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4020678