Method of manufacturing a semiconductor device with flattened mu

Details Method of manufacturing a semiconductor device with flattened mu Method of manufacturing a semiconductor device with flattened mu

1996-02-22

1998-01-06

Niebling, John

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437195, 437228, 437231, H01L 21304

Patent

active

057050287

ABSTRACT:
A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.

REFERENCES:
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5110763 (1992-05-01), Matsumoto
patent: 5246884 (1993-09-01), Jaso et al.
patent: 5252515 (1993-10-01), Tsai et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5272117 (1993-12-01), Roth et al.
patent: 5302233 (1994-04-01), Kim et al.
patent: 5302551 (1994-04-01), Iranmesh et al.
patent: 5310626 (1994-05-01), Fernandes et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5314843 (1994-05-01), Yu et al.
patent: 5328553 (1994-07-01), Poon
patent: 5331117 (1994-07-01), Bryant et al.
patent: 5332694 (1994-07-01), Suzuki
patent: 5334552 (1994-08-01), Homma
patent: 5356513 (1994-10-01), Burke et al.
"Proposal of Introducing Fine Machining Technology into Planarization and Fundamentals of Fine Machining Technology", Break Through Seminar No. 4, pp. 34-46 and 97-102, 2/23-24/93.
Wolf, Stanley, Ph.D., "Silicon Processing for the VLSI Era", vol. 2, Process Integration, Lattice Press, pp. 222-229., 1990.
S. Wolf, "Silicon Processing for the VLSI Era", vol. 2, Process Integration, pp. 229-230, (1990).
"Semiconductor World 1992.10" pp. 43-44, Oct. 1992. (Japanese).

Affiliated with

Also associated with

Rating

Method of manufacturing a semiconductor device with flattened mu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor device with flattened mu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with flattened mu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2325632