Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2008-07-16
2009-10-13
Pizarro, Marcos D. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S597000, C438S675000, C257SE21204, C257SE21424
Reexamination Certificate
active
07601623
ABSTRACT:
A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
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Notification of Reason for Refusal issued by the Japanese Patent Office on Nov. 27, 2007, for Japanese Patent Application No. 2005-051355, and English-language translation thereof.
Koyama Masato
Tsuchiya Yoshinori
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Pizarro Marcos D.
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